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[211.36.80.47]) by mx.google.com with ESMTPS id o5sm32752376pay.5.2013.02.05.15.10.52 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 05 Feb 2013 15:10:53 -0800 (PST) From: Girish K S To: spi-devel-general@lists.sourceforge.net, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] spi: s3c64xx: add gpio quirk for controller Date: Tue, 5 Feb 2013 15:09:43 -0800 Message-Id: <1360105784-12282-4-git-send-email-ks.giri@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1360105784-12282-1-git-send-email-ks.giri@samsung.com> References: <1360105784-12282-1-git-send-email-ks.giri@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130205_181059_822395_A0872EFE X-CRM114-Status: GOOD ( 18.18 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.50 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (girishks2000[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (girishks2000[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds support for spi controllers with dedicated clk/miso/mosi/cs pins. It skips the gpio parsing and initialization for controllers that have dedicated pins. Signed-off-by: Girish K S --- drivers/spi/spi-s3c64xx.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 90770bd..f06bbee 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -36,6 +36,7 @@ #define MAX_SPI_PORTS 3 #define S3C64XX_SPI_QUIRK_POLL (1 << 0) +#define S3C64XX_SPI_QUIRK_GPIO (1 << 1) /* Registers and bit-fields */ @@ -404,14 +405,16 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ /* Deselect the last toggled device */ cs = sdd->tgl_spi->controller_data; - gpio_set_value(cs->line, - spi->mode & SPI_CS_HIGH ? 0 : 1); + if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_GPIO)) + gpio_set_value(cs->line, + spi->mode & SPI_CS_HIGH ? 0 : 1); } sdd->tgl_spi = NULL; } cs = spi->controller_data; - gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); + if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_GPIO)) + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); /* Start the signals */ writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); @@ -503,7 +506,8 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi == spi) sdd->tgl_spi = NULL; - gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); + if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_GPIO)) + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); /* Quiese the signals */ writel(S3C64XX_SPI_SLAVE_SIG_INACT, @@ -842,7 +846,10 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( return ERR_PTR(-ENOMEM); } - cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); + /* In case of dedicated cs pin skip the gpio initialization */ + if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_GPIO)) + cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); + if (!gpio_is_valid(cs->line)) { dev_err(&spi->dev, "chip select gpio is not specified or " "invalid\n"); @@ -883,7 +890,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) return -ENODEV; } - if (!spi_get_ctldata(spi)) { + if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_GPIO)) { err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH, dev_name(&spi->dev)); if (err) { @@ -892,9 +899,11 @@ static int s3c64xx_spi_setup(struct spi_device *spi) cs->line, err); goto err_gpio_req; } - spi_set_ctldata(spi, cs); } + if (!spi_get_ctldata(spi)) + spi_set_ctldata(spi, cs); + sci = sdd->cntrlr_info; spin_lock_irqsave(&sdd->lock, flags); @@ -979,8 +988,11 @@ err_gpio_req: static void s3c64xx_spi_cleanup(struct spi_device *spi) { struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); + struct s3c64xx_spi_driver_data *sdd; + + sdd = spi_master_get_devdata(spi->master); - if (cs) { + if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_GPIO) && cs) { gpio_free(cs->line); if (spi->dev.of_node) kfree(cs); @@ -1107,6 +1119,13 @@ static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd) struct device *dev = &sdd->pdev->dev; int idx, gpio, ret; + /* + * If cs is not controlled by gpio, and + * the SoC uses internal dedicated pins + */ + if (sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_GPIO) + return 0; + /* find gpios for mosi, miso and clock lines */ for (idx = 0; idx < 3; idx++) { gpio = of_get_gpio(dev->of_node, idx); @@ -1133,6 +1152,10 @@ free_gpio: static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd) { unsigned int idx; + + if (sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_GPIO) + return; + for (idx = 0; idx < 3; idx++) gpio_free(sdd->gpios[idx]); }