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[211.36.80.164]) by mx.google.com with ESMTPS id t6sm85719744paz.11.2013.02.13.11.26.52 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Feb 2013 11:26:53 -0800 (PST) From: Girish K S To: spi-devel-general@lists.sourceforge.net, linux-kernel@vger.kernel.org Subject: [PATCH V2 4/5] spi: s3c64xx: Added provision for dedicated cs pin Date: Wed, 13 Feb 2013 11:25:30 -0800 Message-Id: <1360783531-32654-5-git-send-email-ks.giri@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1360783531-32654-1-git-send-email-ks.giri@samsung.com> References: <1360783531-32654-1-git-send-email-ks.giri@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130213_142656_181575_D77EA595 X-CRM114-Status: GOOD ( 18.58 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.52 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (girishks2000[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (girishks2000[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: grant.likely@secretlab.ca, t.figa@samsung.com, broonie@opensource.wolfsonmicro.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The existing driver supports gpio based /cs signal. For controller's that have one device per controller, the slave device's /cs signal might be internally controlled by the chip select bit of slave select register. They are not externally asserted/deasserted using gpio pin. This patch adds support for controllers with dedicated /cs pin. if "cs-gpio" property doesnt exist in a spi dts node, the controller would treat the /cs pin as dedicated. Signed-off-by: Girish K S --- changes in v2: added provision to use either gpio/dedicated pins as chip select drivers/spi/spi-s3c64xx.c | 27 +++++++++++++++++++-------- include/linux/platform_data/spi-s3c64xx.h | 3 +++ 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index a8fe876..15b7ee9 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -416,14 +416,16 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ /* Deselect the last toggled device */ cs = sdd->tgl_spi->controller_data; - gpio_set_value(cs->line, - spi->mode & SPI_CS_HIGH ? 0 : 1); + if (cs->cs_gpio) + gpio_set_value(cs->line, + spi->mode & SPI_CS_HIGH ? 0 : 1); } sdd->tgl_spi = NULL; } cs = spi->controller_data; - gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); + if (cs->cs_gpio) + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); /* Start the signals */ writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); @@ -552,7 +554,8 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi == spi) sdd->tgl_spi = NULL; - gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); + if (cs->cs_gpio) + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); /* Quiese the signals */ writel(S3C64XX_SPI_SLAVE_SIG_INACT, @@ -891,7 +894,12 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( return ERR_PTR(-ENOMEM); } - cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); + if (of_find_property(data_np, "cs-gpio", NULL)) { + /* The CS line is asserted/deasserted by the gpio pin */ + cs->cs_gpio = true; + cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); + } + if (!gpio_is_valid(cs->line)) { dev_err(&spi->dev, "chip select gpio is not specified or invalid\n"); kfree(cs); @@ -931,7 +939,8 @@ static int s3c64xx_spi_setup(struct spi_device *spi) return -ENODEV; } - if (!spi_get_ctldata(spi)) { + /* Request gpio only if cs line is asserted by gpio pins */ + if (cs->cs_gpio) { err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH, dev_name(&spi->dev)); if (err) { @@ -940,9 +949,11 @@ static int s3c64xx_spi_setup(struct spi_device *spi) cs->line, err); goto err_gpio_req; } - spi_set_ctldata(spi, cs); } + if (!spi_get_ctldata(spi)) + spi_set_ctldata(spi, cs); + sci = sdd->cntrlr_info; spin_lock_irqsave(&sdd->lock, flags); @@ -1030,7 +1041,7 @@ static void s3c64xx_spi_cleanup(struct spi_device *spi) { struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); - if (cs) { + if (cs && cs->cs_gpio) { gpio_free(cs->line); if (spi->dev.of_node) kfree(cs); diff --git a/include/linux/platform_data/spi-s3c64xx.h b/include/linux/platform_data/spi-s3c64xx.h index ceba18d..0343d8d 100644 --- a/include/linux/platform_data/spi-s3c64xx.h +++ b/include/linux/platform_data/spi-s3c64xx.h @@ -17,6 +17,8 @@ struct platform_device; * struct s3c64xx_spi_csinfo - ChipSelect description * @fb_delay: Slave specific feedback delay. * Refer to FB_CLK_SEL register definition in SPI chapter. + * @cs_gpio: CS line status, 'true' if CS line is asserted by gpio. + * 'false' if asserted by internal dedicated pin. * @line: Custom 'identity' of the CS line. * * This is per SPI-Slave Chipselect information. @@ -25,6 +27,7 @@ struct platform_device; */ struct s3c64xx_spi_csinfo { u8 fb_delay; + bool cs_gpio; unsigned line; };