From patchwork Wed Feb 13 21:33:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 2139571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 37FED3FCA4 for ; Wed, 13 Feb 2013 21:37:55 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U5jzH-0004eN-Da; Wed, 13 Feb 2013 21:35:31 +0000 Received: from avon.wwwdotorg.org ([2001:470:1f0f:bd7::2]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U5jxR-0003pu-B3 for linux-arm-kernel@lists.infradead.org; Wed, 13 Feb 2013 21:33:39 +0000 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id C17D463FA; Wed, 13 Feb 2013 14:36:40 -0700 (MST) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 11CC0E40DC; Wed, 13 Feb 2013 14:33:34 -0700 (MST) From: Stephen Warren To: Grant Likely , Rob Herring , Olof Johansson , Arnd Bergmann Subject: [PATCH 7/9] ARM: tegra: create a DT header defining GPIO IDs Date: Wed, 13 Feb 2013 14:33:16 -0700 Message-Id: <1360791198-29462-8-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1360791198-29462-1-git-send-email-swarren@wwwdotorg.org> References: <1360791198-29462-1-git-send-email-swarren@wwwdotorg.org> X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130213_163337_820242_F4059B2A X-CRM114-Status: GOOD ( 12.18 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, Stephen Warren , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren All Tegra GPIOs are named after the GPIO bank and GPIO number within the bank. Define a macro to calculate the GPIO ID based on those parameters. Make the macro available via all Tegra .dtsip files. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra-gpio.h | 45 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/tegra114.dtsip | 1 + arch/arm/boot/dts/tegra20.dtsip | 1 + arch/arm/boot/dts/tegra30.dtsip | 1 + 4 files changed, 48 insertions(+) create mode 100644 arch/arm/boot/dts/tegra-gpio.h diff --git a/arch/arm/boot/dts/tegra-gpio.h b/arch/arm/boot/dts/tegra-gpio.h new file mode 100644 index 0000000..aecc570 --- /dev/null +++ b/arch/arm/boot/dts/tegra-gpio.h @@ -0,0 +1,45 @@ +/* + * This header provides constants for binding nvidia,tegra*-gpio. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#include "gpio.h" + +#define TEGRA_GPIO_BANK_ID_A 0 +#define TEGRA_GPIO_BANK_ID_B 1 +#define TEGRA_GPIO_BANK_ID_C 2 +#define TEGRA_GPIO_BANK_ID_D 3 +#define TEGRA_GPIO_BANK_ID_E 4 +#define TEGRA_GPIO_BANK_ID_F 5 +#define TEGRA_GPIO_BANK_ID_G 6 +#define TEGRA_GPIO_BANK_ID_H 7 +#define TEGRA_GPIO_BANK_ID_I 8 +#define TEGRA_GPIO_BANK_ID_J 9 +#define TEGRA_GPIO_BANK_ID_K 10 +#define TEGRA_GPIO_BANK_ID_L 11 +#define TEGRA_GPIO_BANK_ID_M 12 +#define TEGRA_GPIO_BANK_ID_N 13 +#define TEGRA_GPIO_BANK_ID_O 14 +#define TEGRA_GPIO_BANK_ID_P 15 +#define TEGRA_GPIO_BANK_ID_Q 16 +#define TEGRA_GPIO_BANK_ID_R 17 +#define TEGRA_GPIO_BANK_ID_S 18 +#define TEGRA_GPIO_BANK_ID_T 19 +#define TEGRA_GPIO_BANK_ID_U 20 +#define TEGRA_GPIO_BANK_ID_V 21 +#define TEGRA_GPIO_BANK_ID_W 22 +#define TEGRA_GPIO_BANK_ID_X 23 +#define TEGRA_GPIO_BANK_ID_Y 24 +#define TEGRA_GPIO_BANK_ID_Z 25 +#define TEGRA_GPIO_BANK_ID_AA 26 +#define TEGRA_GPIO_BANK_ID_BB 27 +#define TEGRA_GPIO_BANK_ID_CC 28 +#define TEGRA_GPIO_BANK_ID_DD 29 +#define TEGRA_GPIO_BANK_ID_EE 30 + +#define TEGRA_GPIO(bank, offset) \ + ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) diff --git a/arch/arm/boot/dts/tegra114.dtsip b/arch/arm/boot/dts/tegra114.dtsip index d2150f0..356a8af 100644 --- a/arch/arm/boot/dts/tegra114.dtsip +++ b/arch/arm/boot/dts/tegra114.dtsip @@ -1,4 +1,5 @@ #include "skeleton.dtsi" +#include "tegra-gpio.h" / { compatible = "nvidia,tegra114"; diff --git a/arch/arm/boot/dts/tegra20.dtsip b/arch/arm/boot/dts/tegra20.dtsip index 917edd4..1caece9 100644 --- a/arch/arm/boot/dts/tegra20.dtsip +++ b/arch/arm/boot/dts/tegra20.dtsip @@ -1,4 +1,5 @@ #include "skeleton.dtsi" +#include "tegra-gpio.h" / { compatible = "nvidia,tegra20"; diff --git a/arch/arm/boot/dts/tegra30.dtsip b/arch/arm/boot/dts/tegra30.dtsip index d25975e..70b6ac7 100644 --- a/arch/arm/boot/dts/tegra30.dtsip +++ b/arch/arm/boot/dts/tegra30.dtsip @@ -1,4 +1,5 @@ #include "skeleton.dtsi" +#include "tegra-gpio.h" / { compatible = "nvidia,tegra30";