From patchwork Mon Feb 18 05:12:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2155491 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 8C2AC3FDF1 for ; Mon, 18 Feb 2013 05:17:55 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U7J4Z-0001Yh-BW; Mon, 18 Feb 2013 05:15:27 +0000 Received: from mail-pa0-f51.google.com ([209.85.220.51]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U7J35-0000gq-0B for linux-arm-kernel@lists.infradead.org; Mon, 18 Feb 2013 05:13:56 +0000 Received: by mail-pa0-f51.google.com with SMTP id hz1so2599856pad.38 for ; Sun, 17 Feb 2013 21:13:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=nDBJhNF90M/R2Azg2nMtCe0GN6MHwZN/SolB9d4955c=; b=dTgwtG0qRvsFLCo56cHazqy+Vh2S2poKOo9vWg7eF0K0TyZ/OyT9GrhaSgVGet/sNl G3QYIxMZsqcAgxIaU+wVL32N9l0RxzYWdmJdgjLlsraJLQW+32EpHJm5rRgAdqNEUP/v niO/PxcvRjMC+GVLT8chq90ArLYpQVHjVVDW72FrlKRJEHkmBPD7gulK8F29Tbgod2Jo TsYM5mf86tRfVAlcZr+8JUXH8EHeginR3vTXB2Ikva0ORDsYBKbh625GZgpzmavVXfbh XBwjpeb2fLqRcJfV7P8nRqivXxV94xRzqks8EImxQA939FX9pSfdQfU+Yfm/N4VY3L/b CPMw== X-Received: by 10.66.75.200 with SMTP id e8mr32579511paw.72.1361164433682; Sun, 17 Feb 2013 21:13:53 -0800 (PST) Received: from localhost.localdomain ([140.206.155.71]) by mx.google.com with ESMTPS id ni3sm13194880pbc.31.2013.02.17.21.13.45 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 17 Feb 2013 21:13:53 -0800 (PST) From: Haojian Zhuang To: grinberg@compulab.co.il, linus.walleij@linaro.org, linux@arm.linux.org.uk, marek.vasut@gmail.com, robert.jarzmik@free.fr, daniel@caiaq.de, linux-arm-kernel@lists.infradead.org, grant.likely@secretlab.ca, cxie4@marvell.com Subject: [PATCH v3 07/12] gpio: pxa: remove arch related macro Date: Mon, 18 Feb 2013 13:12:33 +0800 Message-Id: <1361164358-5845-8-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1361164358-5845-1-git-send-email-haojian.zhuang@linaro.org> References: <1361164358-5845-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQkSYeukWtKFdIi8WRRoekRTFReN5gG51oQspLXCMIN+ql/N1lK+D+S0LzA6LsG7kBUJoC9Y X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130218_001355_150945_A852ABDC X-CRM114-Status: GOOD ( 10.35 ) X-Spam-Score: 0.4 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.51 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Remove macro CONFIG_ARCH_PXA. Signed-off-by: Haojian Zhuang Acked-by: Linus Walleij --- drivers/gpio/gpio-pxa.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 95561d6..8130e3b 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -568,21 +568,21 @@ static int pxa_gpio_probe(struct platform_device *pdev) } if (!use_of) { -#ifdef CONFIG_ARCH_PXA - irq = gpio_to_irq(0); - irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, - handle_edge_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler); - - irq = gpio_to_irq(1); - irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, - handle_edge_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler); -#endif - - for (irq = gpio_to_irq(gpio_offset); + if (irq0 > 0) { + irq = gpio_to_irq(0); + irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, + handle_edge_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_set_chained_handler(irq0, pxa_gpio_demux_handler); + } + if (irq1 > 0) { + irq = gpio_to_irq(1); + irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, + handle_edge_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_set_chained_handler(irq1, pxa_gpio_demux_handler); + } + for (irq = gpio_to_irq(gpio_offset); irq <= gpio_to_irq(pxa_last_gpio); irq++) { irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, handle_edge_irq);