From patchwork Fri Feb 22 06:44:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 2174741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id EA3353FD4E for ; Fri, 22 Feb 2013 06:48:24 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U8mOE-0007nz-0F; Fri, 22 Feb 2013 06:45:50 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U8mNY-0007j3-Li for linux-arm-kernel@lists.infradead.org; Fri, 22 Feb 2013 06:45:09 +0000 Received: from hqnvupgp06.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Thu, 21 Feb 2013 22:49:58 -0800 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp06.nvidia.com (PGP Universal service); Thu, 21 Feb 2013 22:43:41 -0800 X-PGP-Universal: processed; by hqnvupgp06.nvidia.com on Thu, 21 Feb 2013 22:43:41 -0800 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.297.1; Thu, 21 Feb 2013 22:45:07 -0800 From: Joseph Lo To: Stephen Warren Subject: [PATCH 4/4] ARM: tegra114: bring up secondary CPU for SMP Date: Fri, 22 Feb 2013 14:44:51 +0800 Message-ID: <1361515491-16199-5-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.1.1 In-Reply-To: <1361515491-16199-1-git-send-email-josephl@nvidia.com> References: <1361515491-16199-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130222_014508_838279_A7E92E85 X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The secondary CPU can be brought up by toggling the power in PMC. Then the flow controller will release CPU to go by clearing the reset and clamp signal automatically. Based on the work by: Bo Yan Signed-off-by: Joseph Lo --- arch/arm/mach-tegra/platsmp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 601bd0c..516aab2 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -146,6 +146,12 @@ remove_clamps: return 0; } +static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + cpu = cpu_logical_map(cpu); + return tegra_pmc_cpu_power_on(cpu); +} + static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle) { @@ -153,6 +159,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu, return tegra20_boot_secondary(cpu, idle); if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) return tegra30_boot_secondary(cpu, idle); + if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) + return tegra114_boot_secondary(cpu, idle); return -EINVAL; }