From patchwork Wed Feb 27 02:27:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 2191851 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 370043FD4E for ; Wed, 27 Feb 2013 02:31:13 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UAWkR-00009c-Qe; Wed, 27 Feb 2013 02:27:59 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UAWkO-00008o-2G for linux-arm-kernel@lists.infradead.org; Wed, 27 Feb 2013 02:27:57 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Tue, 26 Feb 2013 18:32:50 -0800 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 26 Feb 2013 18:22:33 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 26 Feb 2013 18:22:33 -0800 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.297.1; Tue, 26 Feb 2013 18:27:52 -0800 From: Joseph Lo To: Stephen Warren Subject: [PATCH V2 1/2] ARM: tegra: pmc: add specific compatible DT string for Tegra30 and Tegra114 Date: Wed, 27 Feb 2013 10:27:42 +0800 Message-ID: <1361932063-13263-1-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.1.1 X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130226_212756_257738_0D868CE2 X-CRM114-Status: GOOD ( 10.09 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The PMC HW is not 100% compatible across all Tegra series. We need to specify each of them in the DT match table. Signed-off-by: Joseph Lo --- V2: * fix the typo and the chip order in DT match table --- arch/arm/mach-tegra/pmc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index d4fdb5f..5d79d34 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -36,6 +36,8 @@ static inline void tegra_pmc_writel(u32 val, u32 reg) #ifdef CONFIG_OF static const struct of_device_id matches[] __initconst = { + { .compatible = "nvidia,tegra114-pmc" }, + { .compatible = "nvidia,tegra30-pmc" }, { .compatible = "nvidia,tegra20-pmc" }, { } };