From patchwork Thu Feb 28 07:19:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2195711 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id B4C96DF2A2 for ; Thu, 28 Feb 2013 07:26:18 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UAxo8-0005Kj-Hb; Thu, 28 Feb 2013 07:21:36 +0000 Received: from mail-pa0-f51.google.com ([209.85.220.51]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UAxmc-0004sg-Hh for linux-arm-kernel@lists.infradead.org; Thu, 28 Feb 2013 07:20:05 +0000 Received: by mail-pa0-f51.google.com with SMTP id hz1so973416pad.10 for ; Wed, 27 Feb 2013 23:20:00 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=Gr42dPSYbwJtpG9TveLGzWyjInBOERA/FTr9Rza8Qkk=; b=VYfDLabxyuaTrtYElfoHRpyjdUcOwArYWHWtIT0GlCSw0OQFwapkteaaqjczhgDw21 wlaszPQqARYXqnAwVf8w14hTRqEth8rrFTdRo2HORVUhPgLELJMCGaqy9hjNMg6/lIbA zGUMUnejykIKI9/aAQF7kxjJEHHd6OZO5TqPSwo+6Kz2+Xnr6rBfJ0DhUNdy84hw9Bvm Ir/SlgrqeYXEMrLecsNhZ+O4POQTV1XnZdhmSHxSusfOiAzRp3kK2/frUMZsatelGHtK cKKvgtNDnOFU5ZbjYP6ByhFSp9ubXFz6EqBIuo6TyKhPtFBXJdkP4xVwz7PVYSrQr1Hk f0LQ== X-Received: by 10.66.162.41 with SMTP id xx9mr11853066pab.168.1362036000543; Wed, 27 Feb 2013 23:20:00 -0800 (PST) Received: from localhost.localdomain ([140.206.155.71]) by mx.google.com with ESMTPS id k7sm8255069paz.13.2013.02.27.23.19.55 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 27 Feb 2013 23:19:59 -0800 (PST) From: Haojian Zhuang To: jone.lixin@huawei.com, arnd@arndb.de, olof@lixom.net, linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/7] document: append hisilicon clock binding Date: Thu, 28 Feb 2013 15:19:24 +0800 Message-Id: <1362035966-17628-5-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1362035966-17628-1-git-send-email-haojian.zhuang@linaro.org> References: <1362035966-17628-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQmaOIUBrANRSdUCNR2V5m5Q4v6rYE3B5yYGYmo52YIbbZouj/eYNGjn4lY16ECE8vBuHw4S X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130228_022002_882989_6A38A995 X-CRM114-Status: GOOD ( 10.26 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.51 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add hisilicon clock binding document for device tree. Signed-off-by: Haojian Zhuang --- .../devicetree/bindings/clock/hisilicon.txt | 73 ++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/hisilicon.txt diff --git a/Documentation/devicetree/bindings/clock/hisilicon.txt b/Documentation/devicetree/bindings/clock/hisilicon.txt new file mode 100644 index 0000000..04fefc3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hisilicon.txt @@ -0,0 +1,73 @@ +Device Tree Clock bindings for arch-vt8500 + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties for mux clocks: + - compatible : Shall be "hisilicon,hi3620-clk-mux". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,hi3620-mux : array of mux register offset & mask bits + +Required properties for Hi3620 gate clocks: + - compatible : Shall be "hisilicon,hi3620-clk-gate". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,hi3620-clkgate : array of enable register offset & enable bit + - hisilicon,hi3620-clkreset : array of reset register offset & enable bit + +Required properties for gate clocks: + - compatible : Shall be "hisilicon,clk-gate". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,clkgate-inverted : bool value. True means that set-to-disable. + +Required properties for clock divider: + - compatible : Shall be "hisilicon,clk-div-table". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - #hisilicon,clkdiv-table-cells : the number of parameters after phandle in + hisilicon,clkdiv-table property. + - hisilicon,clkdiv-table : list of value that are used to configure clock + divider. They're value of phandle, index & divider value. + - hisilicon,clkdiv : array of divider register offset & mask bits. + +Required properties for clock fixed factor divider: + - compatible : Shall be "hisilicon,fixed-factor". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,fixed-factor : array of multiplier & divider. + +For example: + timclk1: clkgate@38 { + compatible = "hisilicon,clk-gate"; + #clock-cells = <0>; + clocks = <&refclk_timer1>; + clock-output-names = "timclk1"; + hisilicon,clkgate-inverted; + hisilicon,clkgate = <0 18>; + }; + + dtable: clkdiv@0 { + #hisilicon,clkdiv-table-cells = <2>; + }; + + div_cfgaxi: clkdiv@2 { + compatible = "hisilicon,clk-div-table"; + #clock-cells = <0>; + clocks = <&div_shareaxi>; + clock-output-names = "cfgAXI_div"; + hisilicon,clkdiv-table = <&dtable 0x01 2>; + hisilicon,clkdiv = <0x100 0x60>; + };