From patchwork Fri Mar 1 06:00:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 2200441 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 11EBFDF24C for ; Fri, 1 Mar 2013 06:03:35 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UBJ1R-0004a8-1S; Fri, 01 Mar 2013 06:00:45 +0000 Received: from mail-pa0-f42.google.com ([209.85.220.42]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UBJ1N-0004Zo-Gi for linux-arm-kernel@lists.infradead.org; Fri, 01 Mar 2013 06:00:42 +0000 Received: by mail-pa0-f42.google.com with SMTP id kq12so1609766pab.1 for ; Thu, 28 Feb 2013 22:00:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=YFck2/8is42eCCP/hUDvPCwY5cSKLbRoWPP6gx94t4c=; b=kBKMGg2OiUFJllgtmwfqO4kDA7bwBsNZ9PbO2IVtCZUOgJ2h6YucgHBqlCSJn4tsxA viLBizU9r0U6/s8aFWq/tg0JGpUOgWGXTkcUuw0yk1qxLNjrHRp7PibSGCLavSBPWrZ3 4XE1JhhH93bJ4hFrgDvauRmQKMU9X1yq45Y8JIZgzgwDvBVKhSBPzKQoUlKQ4Ut165hM sRlsqLbOrx8632wqItSBNJjYt7q2W5N8sHHG9wI0qgLLRRiNw9Lv6qNcENGVTE2dcpts SwtQ+142clHZ9d8tuQAdKCFYdbGvsNjiwhcGM0caxdxmqfXWngPeWNuZ8XKhDjwnah87 GCfw== X-Received: by 10.68.189.234 with SMTP id gl10mr7508309pbc.53.1362117638487; Thu, 28 Feb 2013 22:00:38 -0800 (PST) Received: from pnqlab006.amcc.com ([122.170.124.90]) by mx.google.com with ESMTPS id dx17sm11868936pac.17.2013.02.28.22.00.35 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 28 Feb 2013 22:00:37 -0800 (PST) From: Anup Patel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: add support for 8250/16550 earlyprintk Date: Fri, 1 Mar 2013 11:30:26 +0530 Message-Id: <1362117626-2076-1-git-send-email-anup.patel@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQnqXKegaxtP/AStAphx+N/hya7+/m8GbFKRKQOnvvbf+2JmqQKKDivDuEZ/RjHl4lCCKaLY X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130301_010041_639179_F71BF5F5 X-CRM114-Status: GOOD ( 10.95 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.42 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linaro-dev@lists.linaro.org, Anup Patel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds support for using earlyprintk with 8250/16550 UART ports. The 8250/16550 UART can either have 8-bit or 32-bit aligned registers which is HW vendor dependent. Kernel args for 8-bit aligned regs: earlyprintk=uart8250-8bit, Kernel args for 32-bit aligned regs: earlyprintk=uart8250-16bit, Signed-off-by: Anup Patel --- arch/arm64/kernel/early_printk.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/kernel/early_printk.c b/arch/arm64/kernel/early_printk.c index 7e320a2..d57f300 100644 --- a/arch/arm64/kernel/early_printk.c +++ b/arch/arm64/kernel/early_printk.c @@ -24,11 +24,32 @@ #include #include +#include static void __iomem *early_base; static void (*printch)(char ch); /* + * 8250/16550 (8-bit aligned registers) single character TX. + */ +static void uart8250_8bit_printch(char ch) +{ + while (!(readb_relaxed(early_base + UART_LSR) & UART_LSR_THRE)) + ; + writeb_relaxed(ch, early_base + UART_TX); +} + +/* + * 8250/16550 (32-bit aligned registers) single character TX. + */ +static void uart8250_32bit_printch(char ch) +{ + while (!(readl_relaxed(early_base + (UART_LSR << 2)) & UART_LSR_THRE)) + ; + writel_relaxed(ch, early_base + (UART_TX << 2)); +} + +/* * PL011 single character TX. */ static void pl011_printch(char ch) @@ -47,6 +68,8 @@ struct earlycon_match { static const struct earlycon_match earlycon_match[] __initconst = { { .name = "pl011", .printch = pl011_printch, }, + { .name = "uart8250-8bit", .printch = uart8250_8bit_printch, }, + { .name = "uart8250-32bit", .printch = uart8250_32bit_printch, }, {} };