From patchwork Sun Mar 3 16:22:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 2208481 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 8665FDF215 for ; Sun, 3 Mar 2013 16:26:47 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UCBgF-0002LA-DV; Sun, 03 Mar 2013 16:22:31 +0000 Received: from smtp36.i.mail.ru ([94.100.177.96]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UCBgA-0002Kr-Nk for linux-arm-kernel@lists.infradead.org; Sun, 03 Mar 2013 16:22:28 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail; h=Message-Id:Date:Subject:Cc:To:From; bh=rjZQVJ8VqjzFJDrlSmEvmm2QYhBdJ+d2dIF9iE6cb2o=; b=Uk7jMkyeE4VELdc9fLpIB20o+MmXQmsmjWo/x4BBETjdYgQmbKZx8RoeyOGIjsi/ZorqpaZsvBYsG+KZvwMklTfjxbxmc+K34VPSGAD27Oxo279HI/uF7OWywEAPSPaz; Received: from [188.134.40.128] (port=2469 helo=shc.zet) by smtp36.i.mail.ru with esmtpa (envelope-from ) id 1UCBg3-0004LP-2u; Sun, 03 Mar 2013 20:22:19 +0400 From: Alexander Shiyan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: s3c24xx: Add special bus clock ratio mode support for S3C2410A Date: Sun, 3 Mar 2013 20:22:06 +0400 Message-Id: <1362327726-8193-1-git-send-email-shc_work@mail.ru> X-Mailer: git-send-email 1.7.12.4 X-Spam: Not detected X-Mras: Ok X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130303_112227_244797_E667DA32 X-CRM114-Status: GOOD ( 14.02 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (shc_work[at]mail.ru) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Kukjin Kim , linux-samsung-soc@vger.kernel.org, Arnd Bergmann , Ben Dooks , Alexander Shiyan X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds a special bus clock ratio mode support (1:4:4) for S3C2410A CPU targets. This mode means that the HCLK and PCLK frequency is the same as the FCLK/4. Signed-off-by: Alexander Shiyan --- arch/arm/mach-s3c24xx/cpufreq-s3c2410.c | 36 ++++++++++++++----------- arch/arm/mach-s3c24xx/include/mach/regs-clock.h | 1 + arch/arm/mach-s3c24xx/include/mach/regs-gpio.h | 1 + arch/arm/mach-s3c24xx/s3c2410.c | 11 ++++++-- 4 files changed, 31 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c index cfa0dd8..0890ab7 100644 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c +++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c @@ -24,22 +24,25 @@ #include #include +#include #include #include #include -/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */ - static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) { u32 clkdiv = 0; - if (cfg->divs.h_divisor == 2) - clkdiv |= S3C2410_CLKDIVN_HDIVN; + if (cfg->divs.h_divisor == 4) { + clkdiv = S3C2410_CLKDIVN_HDIVN1; + } else { + if (cfg->divs.h_divisor == 2) + clkdiv = S3C2410_CLKDIVN_HDIVN; - if (cfg->divs.p_divisor != cfg->divs.h_divisor) - clkdiv |= S3C2410_CLKDIVN_PDIVN; + if (cfg->divs.p_divisor != cfg->divs.h_divisor) + clkdiv |= S3C2410_CLKDIVN_PDIVN; + } __raw_writel(clkdiv, S3C2410_CLKDIVN); } @@ -48,27 +51,27 @@ static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) { unsigned long hclk, fclk, pclk; unsigned int hdiv, pdiv; - unsigned long hclk_max; fclk = cfg->freq.fclk; - hclk_max = cfg->max.hclk; - - cfg->freq.armclk = fclk; - - s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n", - __func__, fclk, hclk_max); hdiv = (fclk > cfg->max.hclk) ? 2 : 1; hclk = fclk / hdiv; + pdiv = (hclk > cfg->max.pclk) ? 2 : 1; + pclk = hclk / pdiv; + + if ((samsung_cpu_id == S3C2410_GSTATUS1_2410A) && + ((hclk > cfg->max.hclk) || (pclk > cfg->max.pclk))) { + hdiv = 4; + hclk = fclk / 4; + pdiv = 1; + pclk = fclk / 4; + } if (hclk > cfg->max.hclk) { s3c_freq_dbg("%s: hclk too big\n", __func__); return -EINVAL; } - pdiv = (hclk > cfg->max.pclk) ? 2 : 1; - pclk = hclk / pdiv; - if (pclk > cfg->max.pclk) { s3c_freq_dbg("%s: pclk too big\n", __func__); return -EINVAL; @@ -77,6 +80,7 @@ static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) pdiv *= hdiv; /* record the result */ + cfg->freq.armclk = fclk; cfg->divs.p_divisor = pdiv; cfg->divs.h_divisor = hdiv; diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h index 3415b60..15b707b 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h @@ -62,6 +62,7 @@ #define S3C2410_CLKDIVN_PDIVN (1<<0) #define S3C2410_CLKDIVN_HDIVN (1<<1) +#define S3C2410_CLKDIVN_HDIVN1 (1<<2) #define S3C2410_CLKSLOW_UCLK_OFF (1<<7) #define S3C2410_CLKSLOW_MPLL_OFF (1<<5) diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h index c2ef016..ff8ef6a 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h @@ -571,6 +571,7 @@ #define S3C2410_GSTATUS1_IDMASK (0xffff0000) #define S3C2410_GSTATUS1_2410 (0x32410000) +#define S3C2410_GSTATUS1_2410A (0x32410002) #define S3C2410_GSTATUS1_2412 (0x32412001) #define S3C2410_GSTATUS1_2416 (0x32416003) #define S3C2410_GSTATUS1_2440 (0x32440000) diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c index 9ebef95..c512dac 100644 --- a/arch/arm/mach-s3c24xx/s3c2410.c +++ b/arch/arm/mach-s3c24xx/s3c2410.c @@ -35,6 +35,7 @@ #include #include +#include #include #include @@ -104,8 +105,14 @@ void __init_or_cpufreq s3c2410_setup_clocks(void) /* work out clock scalings */ - hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); - pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); + if ((samsung_cpu_id == S3C2410_GSTATUS1_2410A) && + (tmp & S3C2410_CLKDIVN_HDIVN1)) { + hclk = fclk / 4; + pclk = fclk / 4; + } else { + hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); + pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); + } /* print brieft summary of clocks, etc */