From patchwork Mon Mar 4 22:43:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 2215151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 60703DF2F2 for ; Mon, 4 Mar 2013 22:46:21 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UCe6H-0000lS-FI; Mon, 04 Mar 2013 22:43:17 +0000 Received: from wolverine02.qualcomm.com ([199.106.114.251]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UCe69-0000kF-5l for linux-arm-kernel@lists.infradead.org; Mon, 04 Mar 2013 22:43:09 +0000 X-IronPort-AV: E=Sophos;i="4.84,783,1355126400"; d="scan'208";a="27654213" Received: from pdmz-ns-snip_114_130.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.130]) by wolverine02.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 04 Mar 2013 14:43:05 -0800 Received: from sboyd-linux.qualcomm.com (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 7B3DB10004DF; Mon, 4 Mar 2013 14:43:05 -0800 (PST) From: Stephen Boyd To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] ARM: Consolidate preempt enable/disable assembly into macros Date: Mon, 4 Mar 2013 14:43:02 -0800 Message-Id: <1362436983-28988-2-git-send-email-sboyd@codeaurora.org> X-Mailer: git-send-email 1.7.9.7.1.ge545 In-Reply-To: <1362436983-28988-1-git-send-email-sboyd@codeaurora.org> References: <1362436983-28988-1-git-send-email-sboyd@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130304_174309_442251_7FE6612C X-CRM114-Status: GOOD ( 11.28 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.251 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org We duplicate the same few preempt enable and disable assembly instructions in multiple places in the vfp code. Move the code to a macro in entry-header.S so that we can modify the preempt enable/disable assembly in one place in the future. Signed-off-by: Stephen Boyd --- arch/arm/kernel/entry-header.S | 17 +++++++++++++++++ arch/arm/vfp/entry.S | 20 +++----------------- arch/arm/vfp/vfphw.S | 14 ++------------ 3 files changed, 22 insertions(+), 29 deletions(-) diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 9a8531e..130e6a6 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -163,6 +163,23 @@ .endm #endif /* !CONFIG_THUMB2_KERNEL */ + .macro preempt_enable_no_resched, tsk, cnt +#ifdef CONFIG_PREEMPT_COUNT + get_thread_info \tsk + ldr \cnt, [\tsk, #TI_PREEMPT] @ get preempt count + sub \cnt, \cnt, #1 @ decrement it + str \cnt, [\tsk, #TI_PREEMPT] +#endif + .endm + + .macro preempt_disable, tsk, cnt +#ifdef CONFIG_PREEMPT_COUNT + ldr \cnt, [\tsk, #TI_PREEMPT] @ get preempt count + add \cnt, \cnt, #1 @ increment it + str \cnt, [\tsk, #TI_PREEMPT] +#endif + .endm + /* * These are the registers used in the syscall handler, and allow us to * have in theory up to 7 arguments to a function - r0 to r6. diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index 323ce1a..e528709 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -22,11 +22,7 @@ @ IRQs disabled. @ ENTRY(do_vfp) -#ifdef CONFIG_PREEMPT_COUNT - ldr r4, [r10, #TI_PREEMPT] @ get preempt count - add r11, r4, #1 @ increment it - str r11, [r10, #TI_PREEMPT] -#endif + preempt_disable r10, r4 enable_irq ldr r4, .LCvfp ldr r11, [r10, #TI_CPU] @ CPU number @@ -35,12 +31,7 @@ ENTRY(do_vfp) ENDPROC(do_vfp) ENTRY(vfp_null_entry) -#ifdef CONFIG_PREEMPT_COUNT - get_thread_info r10 - ldr r4, [r10, #TI_PREEMPT] @ get preempt count - sub r11, r4, #1 @ decrement it - str r11, [r10, #TI_PREEMPT] -#endif + preempt_enable_no_resched r10, r4 mov pc, lr ENDPROC(vfp_null_entry) @@ -53,12 +44,7 @@ ENDPROC(vfp_null_entry) __INIT ENTRY(vfp_testing_entry) -#ifdef CONFIG_PREEMPT_COUNT - get_thread_info r10 - ldr r4, [r10, #TI_PREEMPT] @ get preempt count - sub r11, r4, #1 @ decrement it - str r11, [r10, #TI_PREEMPT] -#endif + preempt_enable_no_resched r10, r4 ldr r0, VFP_arch_address str r5, [r0] @ known non-zero value mov pc, r9 @ we have handled the fault diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index dd5e56f..8bae250 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -168,12 +168,7 @@ vfp_hw_state_valid: @ else it's one 32-bit instruction, so @ always subtract 4 from the following @ instruction address. -#ifdef CONFIG_PREEMPT_COUNT - get_thread_info r10 - ldr r4, [r10, #TI_PREEMPT] @ get preempt count - sub r11, r4, #1 @ decrement it - str r11, [r10, #TI_PREEMPT] -#endif + preempt_enable_no_resched r10, r4 mov pc, r9 @ we think we have handled things @@ -192,12 +187,7 @@ look_for_VFP_exceptions: @ not recognised by VFP DBGSTR "not VFP" -#ifdef CONFIG_PREEMPT_COUNT - get_thread_info r10 - ldr r4, [r10, #TI_PREEMPT] @ get preempt count - sub r11, r4, #1 @ decrement it - str r11, [r10, #TI_PREEMPT] -#endif + preempt_enable_no_resched r10, r4 mov pc, lr process_exception: