From patchwork Tue Mar 5 09:29:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Campbell X-Patchwork-Id: 2218381 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 80757DF24C for ; Tue, 5 Mar 2013 09:35:26 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UCoEp-00057T-Of; Tue, 05 Mar 2013 09:32:47 +0000 Received: from smtp.citrix.com ([66.165.176.89]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UCoEm-00056c-5c for linux-arm-kernel@lists.infradead.org; Tue, 05 Mar 2013 09:32:45 +0000 X-IronPort-AV: E=Sophos;i="4.84,786,1355097600"; d="scan'208";a="11147535" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP/TLS/AES128-SHA; 05 Mar 2013 09:32:41 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.2.318.1; Tue, 5 Mar 2013 04:32:41 -0500 Received: from gateway-1.uk.xensource.com ([10.80.16.66] helo=[127.0.0.1]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1UCoEi-0008Gd-0p; Tue, 05 Mar 2013 09:32:40 +0000 Message-ID: <1362475797.8941.67.camel@hastur.hellion.org.uk> Subject: Re: [PATCH LINUX v5] xen: event channel arrays are xen_ulong_t and not unsigned long From: Ian Campbell To: Will Deacon Date: Tue, 5 Mar 2013 09:29:57 +0000 In-Reply-To: <20130305080845.GA19097@mudshark.cambridge.arm.com> References: <1361285327.1051.115.camel@zakaz.uk.xensource.com> <1361360886-2956-1-git-send-email-ian.campbell@citrix.com> <51340ACD.70904@gmail.com> <20130305030436.GA18040@mudshark.cambridge.arm.com> <513596F2.1000701@gmail.com> <20130305080845.GA19097@mudshark.cambridge.arm.com> X-Mailer: Evolution 3.4.4-2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130305_043244_387356_F24A6CD9 X-CRM114-Status: GOOD ( 12.01 ) X-Spam-Score: -7.5 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [66.165.176.89 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.6 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "Keir \(Xen.org\)" , Stefano Stabellini , Nicolas Pitre , Konrad Rzeszutek Wilk , "Tim \(Xen.org\)" , "linux-kernel@vger.kernel.org" , "xen-devel@lists.xen.org" , Jan Beulich , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Tue, 2013-03-05 at 08:08 +0000, Will Deacon wrote: > Cheers Rob, that was enough to reproduce for me. The problem is likely that > CONFIG_AEABI=n, so the ABI doesn't actually mandate even base registers for > 64-bit values in registers. Me too. > Ian -- this would be fixed if you used our atomic64 routines instead of > inventing your own :) I looked and couldn't see an existing 64 bit xchg, was I looking in the wrong place? Ah, wait, I see atomic64_xchg now. But that needs an atomic64_t while I have a xen_ulong_t (which == 64 bits on ARM). This is a kernel<->hypervisor ABI so I can't just change it to an atomic64_t. I suppose I could cast (see below, untested) but that seems rather icky. Ian. diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h index 0e1f59e..e86a1b3 100644 --- a/arch/arm/include/asm/xen/events.h +++ b/arch/arm/include/asm/xen/events.h @@ -2,6 +2,7 @@ #define _ASM_ARM_XEN_EVENTS_H #include +#include enum ipi_vector { XEN_PLACEHOLDER_VECTOR, @@ -15,27 +16,6 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) return raw_irqs_disabled_flags(regs->ARM_cpsr); } -/* - * We cannot use xchg because it does not support 8-byte - * values. However it is safe to use {ldr,dtd}exd directly because all - * platforms which Xen can run on support those instructions. - */ -static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val) -{ - xen_ulong_t oldval; - unsigned int tmp; - - smp_wmb(); - asm volatile("@ xchg_xen_ulong\n" - "1: ldrexd %0, %H0, [%3]\n" - " strexd %1, %2, %H2, [%3]\n" - " teq %1, #0\n" - " bne 1b" - : "=&r" (oldval), "=&r" (tmp) - : "r" (val), "r" (ptr) - : "memory", "cc"); - smp_wmb(); - return oldval; -} +#define xchg_xen_ulong(ptr, val) atomic64_xchg((atomic64_t *)(ptr), (val)) #endif /* _ASM_ARM_XEN_EVENTS_H */