| Message ID | 1362583767-13862-2-git-send-email-maxime.ripard@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hello Maxime, El 06/03/13 12:29, Maxime Ripard escribió: > Commit 0bbeb3c3 ("of serial port driver - add clk_get_rate() support") made > possible to use directly a clock phandle instead of a raw frequency > specified in the clock frequency attribute, so let's use it. Aren't we using the 8250_dw driver since mainline's 1bea07f16d ("ARM: sunxi: Use the Synosys APB UART instead of ns8250") though? That one doesn't seem to have clock phandle support as of today. I have two patches to add support to it and switch the UARTs to "clocks" with a phandle as part of the clock gates series on my tree if you want to have a look. Emilio
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index 8b36abe..791c02a 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi @@ -65,7 +65,7 @@ interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; + clocks = <&osc>; status = "disabled"; }; @@ -75,7 +75,7 @@ interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; + clocks = <&osc>; status = "disabled"; }; };
Commit 0bbeb3c3 ("of serial port driver - add clk_get_rate() support") made possible to use directly a clock phandle instead of a raw frequency specified in the clock frequency attribute, so let's use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm/boot/dts/sunxi.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)