| Message ID | 1363246822-14597-1-git-send-email-dahuang@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 03/14/2013 01:40 AM, Danny Huang wrote: > Add speedo-based process identifictaion for Tegra114. > > Based on the work by: > Alex Frid <afrid@nvidia.com> This code is surprisingly quite a bit simpler than the existing tegra30_speedo.c. Are you sure it's complete? > diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c > @@ -137,6 +138,9 @@ void tegra_init_fuse(void) > tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; > tegra_init_speedo_data = &tegra30_init_speedo_data; > break; > + case TEGRA114: > + tegra_init_speedo_data = &tegra114_init_speedo_data; > + break; Don't you need to set tegra_fuse_spare_bit there just like all the other paths do? > diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c > +#define CORE_PROCESS_CORNERS_NUM 2 > +#define CPU_PROCESS_CORNERS_NUM 2 > + > +enum { > + THRESHOLD_INDEX_0, > + THRESHOLD_INDEX_1, > + THRESHOLD_INDEX_COUNT, > +}; > + > +static const u32 core_process_speedos[THRESHOLD_INDEX_COUNT] > + [CORE_PROCESS_CORNERS_NUM] = { > + {1123, UINT_MAX}, > + {0, UINT_MAX}, > +}; > + > +static const u32 cpu_process_speedos[THRESHOLD_INDEX_COUNT] > + [CPU_PROCESS_CORNERS_NUM] = { > + {1695, UINT_MAX}, > + {0, UINT_MAX}, > +}; Those enums/tables are a lot smaller than Tegra30. I'm surprised if we end up making new chips simpler rather than more complex in this area. Are those tables complete? > +static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold) > +{ > + u32 tmp; > + > + switch (sku) { > + case 0x00: > + case 0x10: > + case 0x05: > + case 0x06: > + tegra_cpu_speedo_id = 1; > + tegra_soc_speedo_id = 0; > + *threshold = THRESHOLD_INDEX_0; > + break; > + > + case 0x03: > + case 0x04: > + tegra_cpu_speedo_id = 2; > + tegra_soc_speedo_id = 1; > + *threshold = THRESHOLD_INDEX_1; > + break; > + > + default: > + pr_err("Tegra114 Unknown SKU %d\n", sku); > + tegra_cpu_speedo_id = 0; > + tegra_soc_speedo_id = 0; > + *threshold = THRESHOLD_INDEX_0; > + break; > + } > + > + if (rev == TEGRA_REVISION_A01) { > + tmp = tegra_fuse_readl(0x270) << 1; > + tmp |= tegra_fuse_readl(0x26c); > + if (!tmp) > + tegra_cpu_speedo_id = 0; > + } > +} That's also a lot simpler than Tegra30. Are all those SKUs really valid for all chip revisions including A01 where the 0x270/0x26c fuses are clear? If life really is this simple, then I should be happy:-) But I just want to check that this code really is accurate. > +void tegra114_init_speedo_data(void) The Tegra30 code has a couple BUILD_BUG_ON() here to ensure that the size of the {cpu,core}_process_speedos arrays match THRESHOLD_INDEX_COUNT. It'd be good to be consistent here. In general, the implementation of tegra114_init_speedo_data() is quite different from that of the existing tegra30_init_speedo_data(). It'd be nice if they were as similar as possible in structure so they could be easily compared. Can you take a look at the two and see if any changes are warranted in this patch?
On Sat, 2013-03-16 at 01:36 +0800, Stephen Warren wrote: > On 03/14/2013 01:40 AM, Danny Huang wrote: > > Add speedo-based process identifictaion for Tegra114. > > > > Based on the work by: > > Alex Frid <afrid@nvidia.com> > > This code is surprisingly quite a bit simpler than the existing > tegra30_speedo.c. Are you sure it's complete? It's complete and working for now. But It may need update if we have more sku/chip revision in the future. > > diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c > > > @@ -137,6 +138,9 @@ void tegra_init_fuse(void) > > tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; > > tegra_init_speedo_data = &tegra30_init_speedo_data; > > break; > > + case TEGRA114: > > + tegra_init_speedo_data = &tegra114_init_speedo_data; > > + break; > > Don't you need to set tegra_fuse_spare_bit there just like all the other > paths do? > There is no need of spare fuse access for Tegra114 for now. > > diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c > > > +#define CORE_PROCESS_CORNERS_NUM 2 > > +#define CPU_PROCESS_CORNERS_NUM 2 > > + > > +enum { > > + THRESHOLD_INDEX_0, > > + THRESHOLD_INDEX_1, > > + THRESHOLD_INDEX_COUNT, > > +}; > > + > > +static const u32 core_process_speedos[THRESHOLD_INDEX_COUNT] > > + [CORE_PROCESS_CORNERS_NUM] = { > > + {1123, UINT_MAX}, > > + {0, UINT_MAX}, > > +}; > > + > > +static const u32 cpu_process_speedos[THRESHOLD_INDEX_COUNT] > > + [CPU_PROCESS_CORNERS_NUM] = { > > + {1695, UINT_MAX}, > > + {0, UINT_MAX}, > > +}; > > Those enums/tables are a lot smaller than Tegra30. I'm surprised if we > end up making new chips simpler rather than more complex in this area. > Are those tables complete? That's currently all I have. I think we can add some more data in the future when needed. > > > +static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold) > > +{ > > + u32 tmp; > > + > > + switch (sku) { > > + case 0x00: > > + case 0x10: > > + case 0x05: > > + case 0x06: > > + tegra_cpu_speedo_id = 1; > > + tegra_soc_speedo_id = 0; > > + *threshold = THRESHOLD_INDEX_0; > > + break; > > + > > + case 0x03: > > + case 0x04: > > + tegra_cpu_speedo_id = 2; > > + tegra_soc_speedo_id = 1; > > + *threshold = THRESHOLD_INDEX_1; > > + break; > > + > > + default: > > + pr_err("Tegra114 Unknown SKU %d\n", sku); > > + tegra_cpu_speedo_id = 0; > > + tegra_soc_speedo_id = 0; > > + *threshold = THRESHOLD_INDEX_0; > > + break; > > + } > > + > > + if (rev == TEGRA_REVISION_A01) { > > + tmp = tegra_fuse_readl(0x270) << 1; > > + tmp |= tegra_fuse_readl(0x26c); > > + if (!tmp) > > + tegra_cpu_speedo_id = 0; > > + } > > +} > > That's also a lot simpler than Tegra30. Are all those SKUs really valid > for all chip revisions including A01 where the 0x270/0x26c fuses are clear? Yes, currently the 0x26c/0x270 value affects all sku of A01 chips. > If life really is this simple, then I should be happy:-) But I just want > to check that this code really is accurate. > > > +void tegra114_init_speedo_data(void) > > The Tegra30 code has a couple BUILD_BUG_ON() here to ensure that the > size of the {cpu,core}_process_speedos arrays match > THRESHOLD_INDEX_COUNT. It'd be good to be consistent here. I'll put the BUILD_BUG_ON back and make them consistent with Tegra30 in next version. Thanks. > > In general, the implementation of tegra114_init_speedo_data() is quite > different from that of the existing tegra30_init_speedo_data(). It'd be > nice if they were as similar as possible in structure so they could be > easily compared. Can you take a look at the two and see if any changes > are warranted in this patch? > -- > To unsubscribe from this list: send the line "unsubscribe linux-tegra" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 92703f9..e40326d 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_TEGRA_PCI) += pcie.o +obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o endif diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index f7db078..e035cd2 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -2,6 +2,7 @@ * arch/arm/mach-tegra/fuse.c * * Copyright (C) 2010 Google, Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * Author: * Colin Cross <ccross@android.com> @@ -137,6 +138,9 @@ void tegra_init_fuse(void) tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; tegra_init_speedo_data = &tegra30_init_speedo_data; break; + case TEGRA114: + tegra_init_speedo_data = &tegra114_init_speedo_data; + break; default: pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id); tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index da78434..aacc00d 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2010 Google, Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * Author: * Colin Cross <ccross@android.com> @@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void); static inline void tegra30_init_speedo_data(void) {} #endif +#ifdef CONFIG_ARCH_TEGRA_114_SOC +void tegra114_init_speedo_data(void); +#else +static inline void tegra114_init_speedo_data(void) {} +#endif + #endif diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c new file mode 100644 index 0000000..1188e7b --- /dev/null +++ b/arch/arm/mach-tegra/tegra114_speedo.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/kernel.h> + +#include "fuse.h" + +#define CORE_PROCESS_CORNERS_NUM 2 +#define CPU_PROCESS_CORNERS_NUM 2 + +enum { + THRESHOLD_INDEX_0, + THRESHOLD_INDEX_1, + THRESHOLD_INDEX_COUNT, +}; + +static const u32 core_process_speedos[THRESHOLD_INDEX_COUNT] + [CORE_PROCESS_CORNERS_NUM] = { + {1123, UINT_MAX}, + {0, UINT_MAX}, +}; + +static const u32 cpu_process_speedos[THRESHOLD_INDEX_COUNT] + [CPU_PROCESS_CORNERS_NUM] = { + {1695, UINT_MAX}, + {0, UINT_MAX}, +}; + +static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold) +{ + u32 tmp; + + switch (sku) { + case 0x00: + case 0x10: + case 0x05: + case 0x06: + tegra_cpu_speedo_id = 1; + tegra_soc_speedo_id = 0; + *threshold = THRESHOLD_INDEX_0; + break; + + case 0x03: + case 0x04: + tegra_cpu_speedo_id = 2; + tegra_soc_speedo_id = 1; + *threshold = THRESHOLD_INDEX_1; + break; + + default: + pr_err("Tegra114 Unknown SKU %d\n", sku); + tegra_cpu_speedo_id = 0; + tegra_soc_speedo_id = 0; + *threshold = THRESHOLD_INDEX_0; + break; + } + + if (rev == TEGRA_REVISION_A01) { + tmp = tegra_fuse_readl(0x270) << 1; + tmp |= tegra_fuse_readl(0x26c); + if (!tmp) + tegra_cpu_speedo_id = 0; + } +} + +void tegra114_init_speedo_data(void) +{ + u32 cpu_speedo_val; + u32 core_speedo_val; + int threshold; + int i; + + rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold); + + cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024; + core_speedo_val = tegra_fuse_readl(0x134); + + for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) + if (cpu_speedo_val < cpu_process_speedos[threshold][i]) + break; + tegra_cpu_process_id = i; + + for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) + if (core_speedo_val < core_process_speedos[threshold][i]) + break; + tegra_core_process_id = i; +}
Add speedo-based process identifictaion for Tegra114. Based on the work by: Alex Frid <afrid@nvidia.com> Signed-off-by: Danny Huang <dahuang@nvidia.com> --- arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/fuse.c | 4 ++ arch/arm/mach-tegra/fuse.h | 7 +++ arch/arm/mach-tegra/tegra114_speedo.c | 100 ++++++++++++++++++++++++++++++++++ 4 files changed, 112 insertions(+) create mode 100644 arch/arm/mach-tegra/tegra114_speedo.c