From patchwork Fri Mar 15 15:11:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 2278471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 143B93FC8A for ; Fri, 15 Mar 2013 15:15:08 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UGWIt-00075n-F6; Fri, 15 Mar 2013 15:12:19 +0000 Received: from mail-pb0-f46.google.com ([209.85.160.46]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UGWIg-00072k-FZ for linux-arm-kernel@lists.infradead.org; Fri, 15 Mar 2013 15:12:08 +0000 Received: by mail-pb0-f46.google.com with SMTP id uo15so3926009pbc.5 for ; Fri, 15 Mar 2013 08:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=21oSPEqu2hUVdBvwJpOfVLnukQgYU0iExEeDaFxqYEY=; b=TGnnr2gJBt8q3e06/okg099ZSpQwvB2m/2GZ7ailS6a9kmEKSKHbvTEsailZwYxPc5 pnG7sfzcpqCXrZWLfkHIOUxXS62b2ieTkGZVAnKUoPQOu6IxyJ25YvECAmOyE65coyEG nzqYyJ8HRnfMPqRxaHvp3AhKQMuHGPxb+kOicp+9yxppai7kyYs0RsrpSytGvrmzGoLY JoWq0PCnr6O4xZ0rBiW7MsTMOAvCXbgBWTSyrKjN9Ugd+RgIXSllUUHsBAhczPObnMpm Zof2hIB3LePSnhhloqPyeFZKlGHom6vTHvsLQRDWFDco7CLqJ9buXmERpU7DFlSUCHem 50Gg== X-Received: by 10.68.76.1 with SMTP id g1mr17040910pbw.12.1363360324795; Fri, 15 Mar 2013 08:12:04 -0700 (PDT) Received: from localhost.localdomain ([59.98.241.67]) by mx.google.com with ESMTPS id kl4sm9200996pbc.31.2013.03.15.08.12.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 15 Mar 2013 08:12:03 -0700 (PDT) From: Prabhakar lad To: LAK , DLOS Subject: [PATCH v6 1/2] ARM: davinci: dm365: add support for v4l2 video display Date: Fri, 15 Mar 2013 20:41:42 +0530 Message-Id: <1363360303-15521-2-git-send-email-prabhakar.csengg@gmail.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1363360303-15521-1-git-send-email-prabhakar.csengg@gmail.com> References: <1363360303-15521-1-git-send-email-prabhakar.csengg@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130315_111206_709580_3D3D35EE X-CRM114-Status: GOOD ( 21.57 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.160.46 listed in list.dnswl.org] 0.8 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [59.98.241.67 listed in dnsbl.sorbs.net] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (prabhakar.csengg[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: "Lad, Prabhakar" , Sekhar Nori , LKML X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Lad, Prabhakar Create platform devices for various video modules like venc,osd, vpbe and v4l2 driver for dm365. Signed-off-by: Lad, Prabhakar --- arch/arm/mach-davinci/board-dm365-evm.c | 4 +- arch/arm/mach-davinci/davinci.h | 2 +- arch/arm/mach-davinci/dm365.c | 203 +++++++++++++++++++++++++++++-- 3 files changed, 195 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index c2d4958..cf77c46 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -564,8 +564,6 @@ static struct davinci_uart_config uart_config __initdata = { static void __init dm365_evm_map_io(void) { - /* setup input configuration for VPFE input devices */ - dm365_set_vpfe_config(&vpfe_cfg); dm365_init(); } @@ -597,6 +595,8 @@ static __init void dm365_evm_init(void) davinci_setup_mmc(0, &dm365evm_mmc_config); + dm365_init_video(&vpfe_cfg, NULL); + /* maybe setup mmc1/etc ... _after_ mmc0 */ evm_init_cpld(); diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 12d544b..1c2670f 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -84,7 +84,7 @@ void __init dm365_init_ks(struct davinci_ks_platform_data *pdata); void __init dm365_init_rtc(void); void dm365_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); -void dm365_set_vpfe_config(struct vpfe_config *cfg); +int __init dm365_init_video(struct vpfe_config *, struct vpbe_config *); /* DM644x function declarations */ void __init dm644x_init(void); diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 6c39805..ec8b06e 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -40,10 +40,16 @@ #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ +#define DM3XX_VDAC_CONFIG 0x01c4002c + +#define DM365_RTC_BASE 0x01c69000 + /* Base of key scan register bank */ #define DM365_KEYSCAN_BASE 0x01c69400 -#define DM365_RTC_BASE 0x01c69000 +#define DM365_OSD_BASE 0x01c71c00 + +#define DM365_VENC_REG_BASE 0x01c71e00 #define DAVINCI_DM365_VC_BASE 0x01d0c000 #define DAVINCI_DMA_VC_TX 2 @@ -56,6 +62,11 @@ #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000 #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000 +#define DM365_VPSS_CLK_CTRL_ADDR 0x44 +#define DM365_VPSS_VENCCLKEN_ENABLE BIT(3) +#define DM365_VPSS_DACCLKEN_ENABLE BIT(4) +#define DM365_VPSS_PLLC2SYSCLK5_ENABLE BIT(5) + static struct pll_data pll1_data = { .num = 1, .phys_base = DAVINCI_PLL1_BASE, @@ -1226,6 +1237,186 @@ static struct platform_device dm365_isif_dev = { }, }; +static struct resource dm365_osd_resources[] = { + { + .start = DM365_OSD_BASE, + .end = DM365_OSD_BASE + 0x100, + .flags = IORESOURCE_MEM, + }, +}; + +static u64 dm365_video_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device dm365_osd_dev = { + .name = DM365_VPBE_OSD_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm365_osd_resources), + .resource = dm365_osd_resources, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dm365_venc_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM365_VENC_REG_BASE, + .end = DM365_VENC_REG_BASE + 0x180, + .flags = IORESOURCE_MEM, + }, + /* vdaccfg registers io space */ + { + .start = DM3XX_VDAC_CONFIG, + .end = DM3XX_VDAC_CONFIG + 4, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource dm365_v4l2_disp_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM365_VENC_REG_BASE, + .end = DM365_VENC_REG_BASE + 0x180, + .flags = IORESOURCE_MEM, + }, +}; + +static int dm365_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type, + int field) +{ + switch (if_type) { + case V4L2_MBUS_FMT_SGRBG8_1X8: + davinci_cfg_reg(DM365_VOUT_FIELD_G81); + davinci_cfg_reg(DM365_VOUT_COUTL_EN); + davinci_cfg_reg(DM365_VOUT_COUTH_EN); + break; + + case V4L2_MBUS_FMT_YUYV10_1X20: + if (field) + davinci_cfg_reg(DM365_VOUT_FIELD); + else + davinci_cfg_reg(DM365_VOUT_FIELD_G81); + davinci_cfg_reg(DM365_VOUT_COUTL_EN); + davinci_cfg_reg(DM365_VOUT_COUTH_EN); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type, + unsigned int pclock) +{ + void __iomem *vpss_clkctl_reg; + u32 val; + + vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(DM365_VPSS_CLK_CTRL_ADDR); + + switch (type) { + case VPBE_ENC_STD: + vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1); + vpss_enable_clock(VPSS_VPBE_CLOCK, 1); + val = DM365_VPSS_VENCCLKEN_ENABLE | DM365_VPSS_DACCLKEN_ENABLE; + break; + + case VPBE_ENC_DV_TIMINGS: + if (pclock <= 27000000) { + vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1); + vpss_enable_clock(VPSS_VPBE_CLOCK, 1); + val = DM365_VPSS_VENCCLKEN_ENABLE | + DM365_VPSS_DACCLKEN_ENABLE; + } else { + /* set sysclk4 to output 74.25 MHz from pll1 */ + val = DM365_VPSS_PLLC2SYSCLK5_ENABLE | + DM365_VPSS_DACCLKEN_ENABLE | + DM365_VPSS_VENCCLKEN_ENABLE; + } + break; + + default: + return -EINVAL; + } + writel(val, vpss_clkctl_reg); + + return 0; +} + +static struct platform_device dm365_vpbe_display = { + .name = "vpbe-v4l2", + .id = -1, + .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources), + .resource = dm365_v4l2_disp_resources, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct venc_platform_data dm365_venc_pdata = { + .setup_pinmux = dm365_vpbe_setup_pinmux, + .setup_clock = dm365_venc_setup_clock, +}; + +static struct platform_device dm365_venc_dev = { + .name = DM365_VPBE_VENC_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm365_venc_resources), + .resource = dm365_venc_resources, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = (void *)&dm365_venc_pdata, + }, +}; + +static struct platform_device dm365_vpbe_dev = { + .name = "vpbe_controller", + .id = -1, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +int __init dm365_init_video(struct vpfe_config *vpfe_cfg, + struct vpbe_config *vpbe_cfg) +{ + if (vpfe_cfg || vpbe_cfg) + platform_device_register(&dm365_vpss_device); + + if (vpfe_cfg) { + vpfe_capture_dev.dev.platform_data = vpfe_cfg; + /* Add isif clock alias */ + clk_add_alias("master", dm365_isif_dev.name, + "vpss_master", NULL); + platform_device_register(&dm365_isif_dev); + platform_device_register(&vpfe_capture_dev); + } + if (vpbe_cfg) { + dm365_vpbe_dev.dev.platform_data = vpbe_cfg; + platform_device_register(&dm365_osd_dev); + platform_device_register(&dm365_venc_dev); + platform_device_register(&dm365_vpbe_dev); + platform_device_register(&dm365_vpbe_display); + } + + return 0; +} + static int __init dm365_init_devices(void) { if (!cpu_is_davinci_dm365()) @@ -1239,16 +1430,6 @@ static int __init dm365_init_devices(void) clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev), NULL, &dm365_emac_device.dev); - /* Add isif clock alias */ - clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL); - platform_device_register(&dm365_vpss_device); - platform_device_register(&dm365_isif_dev); - platform_device_register(&vpfe_capture_dev); return 0; } postcore_initcall(dm365_init_devices); - -void dm365_set_vpfe_config(struct vpfe_config *cfg) -{ - vpfe_capture_dev.dev.platform_data = cfg; -}