From patchwork Fri Mar 15 19:36:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerlando Falauto X-Patchwork-Id: 2280231 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id D4EA7DF24C for ; Fri, 15 Mar 2013 19:39:50 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UGaRM-0003B0-LF; Fri, 15 Mar 2013 19:37:20 +0000 Received: from mail-de.keymile.com ([195.8.104.1]) by merlin.infradead.org with smtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UGaR0-00037x-0u for linux-arm-kernel@lists.infradead.org; Fri, 15 Mar 2013 19:37:02 +0000 Received: from mailrelay.de.keymile.net ([10.9.1.54]) by eSafe SMTP Relay 1363351032; Fri, 15 Mar 2013 20:36:53 +0100 Received: from chber1-10555x.ch.keymile.net ([172.31.40.82]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id r2FJYwsG008219; Fri, 15 Mar 2013 20:35:06 +0100 (MET) From: Gerlando Falauto To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] genirq: move mask_cache into struct irq_chip_type Date: Fri, 15 Mar 2013 20:36:15 +0100 Message-Id: <1363376175-22312-3-git-send-email-gerlando.falauto@keymile.com> X-Mailer: git-send-email 1.7.10.1 In-Reply-To: <1363376175-22312-1-git-send-email-gerlando.falauto@keymile.com> References: <1363277430-21325-1-git-send-email-holger.brunck@keymile.com><1363376175-22312-1-git-send-email-gerlando.falauto@keymile.com> X-ESAFE-STATUS: [srvhellgate.de.keymile.net] Mail allowed X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130315_153658_503088_C9270342 X-CRM114-Status: GOOD ( 17.62 ) X-Spam-Score: -5.0 (-----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-5.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [195.8.104.1 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -2.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Andrew Lunn , Jason Cooper , Nicolas Pitre , Simon Guinot , Holger Brunck , Gerlando Falauto , Ben Dooks , Thomas Gleixner , Joey Oravec , Simon Guinot , Lennert Buytenhek X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This fixes a regression introduced by e59347a "arm: orion: Use generic irq chip". The same interrupt mask cache (stored within struct irq_chip_generic) is shared between all the irq_chip_type instances. As each irq_chip_type can use a distinct mask register, sharing a single mask cache may not be correct. For instance in the case of Orion SoCs, which have separate mask registers for edge and level interrupts. This patch moves mask_cache from struct irq_chip_generic into struct irq_chip_type. Note that the interrupt support for Samsung SoCs is also slightly affected. Since there are also cases where all irq_chip_type instances share a common mask register, introduce a pointer to the mask register cache and a new flag IRQ_GC_SEPARATE_MASK_REGISTERS to explicitly enable this separate treatment. When this flag is not set, pointers for all irq_chip_type instances point to the the mask register for the first instance so essentially the old behavior is retained. Reported-by: Joey Oravec Signed-off-by: Simon Guinot Signed-off-by: Holger Brunck Signed-off-by: Gerlando Falauto --- arch/arm/plat-orion/gpio.c | 3 ++- arch/arm/plat-samsung/irq-vic-timer.c | 6 ++++-- arch/mips/jz4740/irq.c | 3 ++- drivers/gpio/gpio-mvebu.c | 23 ++++++++++++++--------- include/linux/irq.h | 7 +++++-- kernel/irq/generic-chip.c | 30 +++++++++++++++++++++--------- 6 files changed, 48 insertions(+), 24 deletions(-) diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index c29ee7e..a4dc04a 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -522,7 +522,8 @@ void __init orion_gpio_init(struct device_node *np, ct->handler = handle_edge_irq; ct->chip.name = ochip->chip.label; - irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, + irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE | + IRQ_GC_SEPARATE_MASK_REGISTERS, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); /* Setup irq domain on top of the generic chip. */ diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index f980cf3..a37ded2 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -37,9 +37,11 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) static void s3c_irq_timer_ack(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_irq_chip_type(d); + u32 mask = (1 << 5) << (d->irq - gc->irq_base); - irq_reg_writel(mask | gc->mask_cache, gc->reg_base); + irq_reg_writel(mask | *ct->pmask_cache, gc->reg_base); } /** @@ -89,7 +91,7 @@ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq) irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST | IRQ_NOPROBE, 0); /* Clear the upper bits of the mask_cache*/ - s3c_tgc->mask_cache &= 0x1f; + *ct->pmask_cache &= 0x1f; for (i = 0; i < num; i++, timer_irq++) { irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer); diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c index fc57ded..228ee33 100644 --- a/arch/mips/jz4740/irq.c +++ b/arch/mips/jz4740/irq.c @@ -68,7 +68,8 @@ void jz4740_irq_suspend(struct irq_data *data) void jz4740_irq_resume(struct irq_data *data) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); - jz4740_irq_set_mask(gc, gc->mask_cache); + struct irq_chip_type *ct = irq_data_get_irq_chip_type(data); + jz4740_irq_set_mask(gc, *ct->pmask_cache); } static struct irqaction jz4740_cascade_action = { diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c index 6819d63..31ae5c4 100644 --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c @@ -301,48 +301,52 @@ static void mvebu_gpio_irq_ack(struct irq_data *d) static void mvebu_gpio_edge_irq_mask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache &= ~mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); + *ct->pmask_cache &= ~mask; + writel_relaxed(*ct->pmask_cache, mvebu_gpioreg_edge_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache |= mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); + *ct->pmask_cache |= mask; + writel_relaxed(*ct->pmask_cache, mvebu_gpioreg_edge_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_level_irq_mask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache &= ~mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); + *ct->pmask_cache &= ~mask; + writel_relaxed(*ct->pmask_cache, mvebu_gpioreg_level_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_level_irq_unmask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache |= mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); + *ct->pmask_cache |= mask; + writel_relaxed(*ct->pmask_cache, mvebu_gpioreg_level_mask(mvchip)); irq_gc_unlock(gc); } @@ -649,7 +653,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev) ct->handler = handle_edge_irq; ct->chip.name = mvchip->chip.label; - irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0, + irq_setup_generic_chip(gc, IRQ_MSK(ngpios), + IRQ_GC_SEPARATE_MASK_REGISTERS, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); /* Setup irq domain on top of the generic chip. */ diff --git a/include/linux/irq.h b/include/linux/irq.h index fdf2c4a..063fffb 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -636,6 +636,8 @@ struct irq_chip_regs { * @regs: Register offsets for this chip * @handler: Flow handler associated with this chip * @type: Chip can handle these flow types + * @mask_cache: Cached mask register + * @pmask_cache: Pointer to cached mask register * * A irq_generic_chip can have several instances of irq_chip_type when * it requires different functions and register offsets for different @@ -646,6 +648,8 @@ struct irq_chip_type { struct irq_chip_regs regs; irq_flow_handler_t handler; u32 type; + u32 mask_cache; + u32 *pmask_cache; }; /** @@ -654,7 +658,6 @@ struct irq_chip_type { * @reg_base: Register base address (virtual) * @irq_base: Interrupt base nr for this chip * @irq_cnt: Number of interrupts handled by this chip - * @mask_cache: Cached mask register * @type_cache: Cached type register * @polarity_cache: Cached polarity register * @wake_enabled: Interrupt can wakeup from suspend @@ -675,7 +678,6 @@ struct irq_chip_generic { void __iomem *reg_base; unsigned int irq_base; unsigned int irq_cnt; - u32 mask_cache; u32 type_cache; u32 polarity_cache; u32 wake_enabled; @@ -696,6 +698,7 @@ struct irq_chip_generic { enum irq_gc_flags { IRQ_GC_INIT_MASK_CACHE = 1 << 0, IRQ_GC_INIT_NESTED_LOCK = 1 << 1, + IRQ_GC_SEPARATE_MASK_REGISTERS = 1 << 2, }; /* Generic chip callback functions */ diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 0e6ba78..3daeed3 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -39,7 +39,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d) irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.disable); - gc->mask_cache &= ~mask; + *ct->pmask_cache &= ~mask; irq_gc_unlock(gc); } @@ -57,8 +57,8 @@ void irq_gc_mask_set_bit(struct irq_data *d) u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache |= mask; - irq_reg_writel(gc->mask_cache, gc->reg_base + ct->regs.mask); + *ct->pmask_cache |= mask; + irq_reg_writel(*ct->pmask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } @@ -76,8 +76,8 @@ void irq_gc_mask_clr_bit(struct irq_data *d) u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache &= ~mask; - irq_reg_writel(gc->mask_cache, gc->reg_base + ct->regs.mask); + *ct->pmask_cache &= ~mask; + irq_reg_writel(*ct->pmask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } @@ -96,7 +96,7 @@ void irq_gc_unmask_enable_reg(struct irq_data *d) irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + ct->regs.enable); - gc->mask_cache |= mask; + *ct->pmask_cache |= mask; irq_gc_unlock(gc); } @@ -246,9 +246,21 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, list_add_tail(&gc->list, &gc_list); raw_spin_unlock(&gc_lock); - /* Init mask cache ? */ - if (flags & IRQ_GC_INIT_MASK_CACHE) - gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask); + for (i = 0; i < gc->num_ct; i++) { + if (flags & IRQ_GC_SEPARATE_MASK_REGISTERS) + /* Define mask cache pointer */ + ct[i].pmask_cache = &ct[i].mask_cache; + else + /* They all point to the same mask cache */ + ct[i].pmask_cache = &ct[0].mask_cache; + + /* Init mask cache ? */ + if ((flags & IRQ_GC_INIT_MASK_CACHE) + && ((flags & IRQ_GC_SEPARATE_MASK_REGISTER) + || (i == 0))) + *ct[i].pmask_cache = + irq_reg_readl(gc->reg_base + ct[i].regs.mask); + } for (i = gc->irq_base; msk; msk >>= 1, i++) { if (!(msk & 0x01))