From patchwork Mon Mar 18 14:00:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerlando Falauto X-Patchwork-Id: 2293481 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 7D3C4DF215 for ; Mon, 18 Mar 2013 15:14:28 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UHbik-0007l5-Vy; Mon, 18 Mar 2013 15:11:31 +0000 Received: from mail-de.keymile.com ([195.8.104.1]) by merlin.infradead.org with smtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UHacm-0007BI-56 for linux-arm-kernel@lists.infradead.org; Mon, 18 Mar 2013 14:01:21 +0000 Received: from mailrelay.de.keymile.net ([10.9.1.54]) by eSafe SMTP Relay 1363609782; Mon, 18 Mar 2013 15:01:11 +0100 Received: from chber1-10555x.ch.keymile.net ([172.31.40.82]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id r2IDxIsH027459; Mon, 18 Mar 2013 14:59:24 +0100 (MET) From: Gerlando Falauto To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/9] gpio: mvebu: convert to usage of *pmask_cache within irq_chip_type Date: Mon, 18 Mar 2013 15:00:49 +0100 Message-Id: <1363615255-18200-4-git-send-email-gerlando.falauto@keymile.com> X-Mailer: git-send-email 1.7.10.1 In-Reply-To: <1363615255-18200-1-git-send-email-gerlando.falauto@keymile.com> References: <1363277430-21325-1-git-send-email-holger.brunck@keymile.com><1363615255-18200-1-git-send-email-gerlando.falauto@keymile.com> X-ESAFE-STATUS: [srvhellgate.de.keymile.net] Mail allowed X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130318_100116_714716_728D56AD X-CRM114-Status: UNSURE ( 7.58 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -5.1 (-----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-5.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [195.8.104.1 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -2.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Andrew Lunn , Jason Cooper , Nicolas Pitre , Holger Brunck , Gerlando Falauto , Ben Dooks , Thomas Gleixner , Joey Oravec , Simon Guinot , Lennert Buytenhek X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Since we have now introduced pmask_cache within irq_chip_type to also handle per-chip-type mask registers, convert gpio-mvebu driver to use this new pointer. Signed-off-by: Gerlando Falauto --- drivers/gpio/gpio-mvebu.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c index 456663c..81384f4 100644 --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c @@ -302,48 +302,52 @@ static void mvebu_gpio_irq_ack(struct irq_data *d) static void mvebu_gpio_edge_irq_mask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache &= ~mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); + *ct->pmask_cache &= ~mask; + writel_relaxed(*ct->pmask_cache, mvebu_gpioreg_edge_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache |= mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); + *ct->pmask_cache |= mask; + writel_relaxed(*ct->pmask_cache, mvebu_gpioreg_edge_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_level_irq_mask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache &= ~mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); + *ct->pmask_cache &= ~mask; + writel_relaxed(*ct->pmask_cache, mvebu_gpioreg_level_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_level_irq_unmask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); - gc->mask_cache |= mask; - writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); + *ct->pmask_cache |= mask; + writel_relaxed(*ct->pmask_cache, mvebu_gpioreg_level_mask(mvchip)); irq_gc_unlock(gc); }