From patchwork Tue Mar 26 15:12:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Kukjin X-Patchwork-Id: 2391751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 36BBA3FD8C for ; Thu, 4 Apr 2013 10:43:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UNhe4-0003vU-DW for patchwork-linux-arm@patchwork.kernel.org; Thu, 04 Apr 2013 10:43:52 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UNhbX-0005GD-FV; Thu, 04 Apr 2013 10:41:15 +0000 Received: from mail-pd0-f175.google.com ([209.85.192.175]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UNhau-0004yo-Ro for linux-arm-kernel@lists.infradead.org; Thu, 04 Apr 2013 10:40:38 +0000 Received: by mail-pd0-f175.google.com with SMTP id g10so1142339pdj.20 for ; Thu, 04 Apr 2013 03:40:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=iAFrGEsrNRVjPYBGaUbqPjy3uKiTqSA9JuPQLjxwIkE=; b=EyTj5aDc1iat3Xtxvum0ImjMAZQlgezuHZr5ShEPXaPQlgNtq/ZYTp75NEQMIOAYbH BjZXaZcmesGx77eW1JneCk8rfLGzBvVcwawktMZpn2ooSetgClNpM8ksmF8GkR2P9AlI Qjz0YrZ40LV2uE2q/Tm3G2Ga/guMrqh+rJgmWI1L5vjMHdH+TZrlio3f5Bj6ZooiMfTO qhHP+9hFtXbm5NPJTu2KSLxAfznwDPkHfxBJZSnJwNSaJjibE+hW4z/qST7+3AhjZmBq Mvl6898NTnhZu5VwTARQqhX9yU7mTuNb1pE5VXAS2GGgNz0AOWunddTRKEP2VIDdv1Dt kcQQ== X-Received: by 10.68.231.70 with SMTP id te6mr7834587pbc.159.1365072035060; Thu, 04 Apr 2013 03:40:35 -0700 (PDT) Received: from localhost.localdomain ([121.136.168.198]) by mx.google.com with ESMTPS id ef3sm10937823pad.20.2013.04.04.03.40.32 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 04 Apr 2013 03:40:34 -0700 (PDT) From: Kukjin Kim To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] pinctrl: exynos5440: add gpio interrupt support Date: Wed, 27 Mar 2013 00:12:33 +0900 Message-Id: <1364310754-3692-3-git-send-email-kgene.kim@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1364310754-3692-1-git-send-email-kgene.kim@samsung.com> References: <1364310754-3692-1-git-send-email-kgene.kim@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130404_064037_073908_2915803A X-CRM114-Status: GOOD ( 21.53 ) X-Spam-Score: 2.3 (++) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.192.175 listed in list.dnswl.org] 0.8 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [121.136.168.198 listed in dnsbl.sorbs.net] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (kgene.kim[at]gmail.com) 3.4 DATE_IN_PAST_96_XX Date: is 96 hours or more before Received: date -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Kukjin Kim , Linus Walleij , Thomas Abraham X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Thomas Abraham Exynos5440 supports gpio interrupts on gpios 16 to 23. The eight interrupt lines originating from the pin-controller are connected to the gic. Add irq-chip support for these interrupts. Signed-off-by: Thomas Abraham Cc: Linus Walleij Signed-off-by: Kukjin Kim --- drivers/pinctrl/pinctrl-exynos5440.c | 142 ++++++++++++++++++++++++++++++++++ 1 files changed, 142 insertions(+), 0 deletions(-) diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c index 96cb1e9..b5c5014 100644 --- a/drivers/pinctrl/pinctrl-exynos5440.c +++ b/drivers/pinctrl/pinctrl-exynos5440.c @@ -20,6 +20,9 @@ #include #include #include +#include +#include +#include #include "core.h" /* EXYNOS5440 GPIO and Pinctrl register offsets */ @@ -37,6 +40,7 @@ #define GPIO_DS1 0x2C #define EXYNOS5440_MAX_PINS 23 +#define EXYNOS5440_MAX_GPIO_INT 8 #define PIN_NAME_LENGTH 10 #define GROUP_SUFFIX "-grp" @@ -109,6 +113,7 @@ struct exynos5440_pmx_func { struct exynos5440_pinctrl_priv_data { void __iomem *reg_base; struct gpio_chip *gc; + struct irq_domain *irq_domain; const struct exynos5440_pin_group *pin_groups; unsigned int nr_groups; @@ -116,6 +121,16 @@ struct exynos5440_pinctrl_priv_data { unsigned int nr_functions; }; +/** + * struct exynos5440_gpio_intr_data: private data for gpio interrupts. + * @priv: driver's private runtime data. + * @gpio_int: gpio interrupt number. + */ +struct exynos5440_gpio_intr_data { + struct exynos5440_pinctrl_priv_data *priv; + unsigned int gpio_int; +}; + /* list of all possible config options supported */ static struct pin_config { char *prop_cfg; @@ -598,6 +613,22 @@ static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offse return 0; } +/* gpiolib gpio_to_irq callback function */ +static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +{ + struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); + unsigned int virq; + + if (offset < 16 || offset > 23) + return -ENXIO; + + if (!priv->irq_domain) + return -ENXIO; + + virq = irq_create_mapping(priv->irq_domain, offset - 16); + return virq ? : -ENXIO; +} + /* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */ static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev, struct device_node *cfg_np, unsigned int **pin_list, @@ -821,6 +852,7 @@ static int exynos5440_gpiolib_register(struct platform_device *pdev, gc->get = exynos5440_gpio_get; gc->direction_input = exynos5440_gpio_direction_input; gc->direction_output = exynos5440_gpio_direction_output; + gc->to_irq = exynos5440_gpio_to_irq; gc->label = "gpiolib-exynos5440"; gc->owner = THIS_MODULE; ret = gpiochip_add(gc); @@ -845,6 +877,110 @@ static int exynos5440_gpiolib_unregister(struct platform_device *pdev, return 0; } +static void exynos5440_gpio_irq_unmask(struct irq_data *irqd) +{ + struct exynos5440_pinctrl_priv_data *d; + unsigned long gpio_int; + + d = irq_data_get_irq_chip_data(irqd); + gpio_int = readl(d->reg_base + GPIO_INT); + gpio_int |= 1 << irqd->hwirq; + writel(gpio_int, d->reg_base + GPIO_INT); +} + +static void exynos5440_gpio_irq_mask(struct irq_data *irqd) +{ + struct exynos5440_pinctrl_priv_data *d; + unsigned long gpio_int; + + d = irq_data_get_irq_chip_data(irqd); + gpio_int = readl(d->reg_base + GPIO_INT); + gpio_int &= ~(1 << irqd->hwirq); + writel(gpio_int, d->reg_base + GPIO_INT); +} + +/* irq_chip for gpio interrupts */ +static struct irq_chip exynos5440_gpio_irq_chip = { + .name = "exynos5440_gpio_irq_chip", + .irq_unmask = exynos5440_gpio_irq_unmask, + .irq_mask = exynos5440_gpio_irq_mask, +}; + +/* interrupt handler for GPIO interrupts 0..7 */ +static irqreturn_t exynos5440_gpio_irq(int irq, void *data) +{ + struct exynos5440_gpio_intr_data *intd = data; + struct exynos5440_pinctrl_priv_data *d = intd->priv; + int virq; + + virq = irq_linear_revmap(d->irq_domain, intd->gpio_int); + if (!virq) + return IRQ_NONE; + generic_handle_irq(virq); + return IRQ_HANDLED; +} + +static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct exynos5440_pinctrl_priv_data *d = h->host_data; + + irq_set_chip_data(virq, d); + irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip, + handle_level_irq); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +/* irq domain callbacks for gpio interrupt controller */ +static const struct irq_domain_ops exynos5440_gpio_irqd_ops = { + .map = exynos5440_gpio_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +/* setup handling of gpio interrupts */ +static int exynos5440_gpio_irq_init(struct platform_device *pdev, + struct exynos5440_pinctrl_priv_data *priv) +{ + struct device *dev = &pdev->dev; + struct exynos5440_gpio_intr_data *intd; + int i, irq, ret; + + intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT, + GFP_KERNEL); + if (!intd) { + dev_err(dev, "failed to allocate memory for gpio intr data\n"); + return -ENOMEM; + } + + for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) { + irq = irq_of_parse_and_map(dev->of_node, i); + if (irq <= 0) { + dev_err(dev, "irq parsing failed\n"); + return -EINVAL; + } + + intd->gpio_int = i; + intd->priv = priv; + ret = devm_request_irq(dev, irq, exynos5440_gpio_irq, + 0, dev_name(dev), intd++); + if (ret) { + dev_err(dev, "irq request failed\n"); + return -ENXIO; + } + } + + priv->irq_domain = irq_domain_add_linear(dev->of_node, + EXYNOS5440_MAX_GPIO_INT, + &exynos5440_gpio_irqd_ops, priv); + if (!priv->irq_domain) { + dev_err(dev, "failed to create irq domain\n"); + return -ENXIO; + } + + return 0; +} + static int exynos5440_pinctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -883,6 +1019,12 @@ static int exynos5440_pinctrl_probe(struct platform_device *pdev) return ret; } + ret = exynos5440_gpio_irq_init(pdev, priv); + if (ret) { + dev_err(dev, "failed to setup gpio interrupts\n"); + return ret; + } + platform_set_drvdata(pdev, priv); dev_info(dev, "EXYNOS5440 pinctrl driver registered\n"); return 0;