| Message ID | 1364901583-24867-3-git-send-email-josephl@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 04/02/2013 05:19 AM, Joseph Lo wrote: > Adding the clock sources of PMC into DTS for Tegra20 and Tegra30. Why only Tegra20 and Tegra30; don't you need to make the exact same changes to tegra114-dalmore.dts and tegra114-pluto.dts? (I think the answer is yes, you do). > diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi > index cb73e62..4c107e6 100644 > --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi > +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi > @@ -8,6 +8,19 @@ > reg = <0x00000000 0x20000000>; > }; > > + clocks { ... > + }; > + > host1x { The node order is wrong here. The order should be: 1) Any nodes that existed in any included file, in the same order as they existed in the included file. 2) Any new nodes that have a reg property, sorted by reg property. 3) Any new nodes without a reg property, sorted alpha-numerically by node name. So in this file for example, the new nod should exist between sdhci@c8000600 and sound. This same comment applies to every file in this patch.
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index cb73e62..4c107e6 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -8,6 +8,19 @@ reg = <0x00000000 0x20000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + host1x { hdmi { vdd-supply = <&hdmi_vdd_reg>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 5fb0888..6e6899a 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -10,6 +10,19 @@ reg = <0x00000000 0x40000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + host1x { hdmi { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 43fd28b..54b05b2 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -10,6 +10,19 @@ reg = <0x00000000 0x20000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + host1x { hdmi { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 4f810a5..3b347b8 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -10,6 +10,19 @@ reg = <0x00000000 0x40000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + host1x { hdmi { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 6e9d91f..0c7bc18 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -8,6 +8,19 @@ reg = <0x00000000 0x20000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + host1x { hdmi { vdd-supply = <&hdmi_vdd_reg>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 955bf49..b265ebd 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -10,6 +10,19 @@ reg = <0x00000000 0x40000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + host1x { hdmi { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 3f8ae10..157a2cd 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -10,6 +10,19 @@ reg = <0x00000000 0x40000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + host1x { hdmi { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 87e2d85..87632df 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -10,6 +10,19 @@ reg = <0x00000000 0x20000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + host1x { hdmi { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 26c1134..5fc661d 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -419,6 +419,8 @@ pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car 110>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; }; memory-controller@7000f000 { diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 0a2cd24..c3e0f25 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -10,6 +10,19 @@ reg = <0x80000000 0x80000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 11204e1..eeea511 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -31,6 +31,19 @@ reg = <0x80000000 0x40000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 6042cc1..15ded60 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -428,6 +428,8 @@ pmc { compatible = "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car 218>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; }; memory-controller {
Adding the clock sources of PMC into DTS for Tegra20 and Tegra30. Signed-off-by: Joseph Lo <josephl@nvidia.com> --- V3: * add clk32k_in as one of the PMC clock source. * add a fixed clock of clk32k_in for Tegra20 & Tegra30 V2: * new in this change --- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 13 +++++++++++++ arch/arm/boot/dts/tegra20-harmony.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra20-paz00.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra20-tamonten.dtsi | 13 +++++++++++++ arch/arm/boot/dts/tegra20-trimslice.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra20-ventana.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra20-whistler.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 2 ++ arch/arm/boot/dts/tegra30-beaver.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra30-cardhu.dtsi | 13 +++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 2 ++ 12 files changed, 134 insertions(+)