From patchwork Tue Apr 2 12:19:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trent Piepho X-Patchwork-Id: 2377781 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 125213FD8C for ; Tue, 2 Apr 2013 12:23:29 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UN0Cp-0001pm-ND; Tue, 02 Apr 2013 12:20:51 +0000 Received: from mail-da0-x231.google.com ([2607:f8b0:400e:c00::231]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UN0C4-0001cb-Pj for linux-arm-kernel@lists.infradead.org; Tue, 02 Apr 2013 12:20:05 +0000 Received: by mail-da0-f49.google.com with SMTP id t11so168661daj.36 for ; Tue, 02 Apr 2013 05:20:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=OZoY8AMkhXpit7TjgHYXYLXarY8NO4Yaw0RRsl09HyY=; b=g1BfflXynYoQGTU7nf6qxldZ5WtTMjbeRCqXuwc7I5k29LZN/cBJYdsSiI7rrx0nA0 aoX9SuMwUKJnNz+urFDpI/ROvrqQH8uJltvARvG9Zt8AKQVTIQXen41DiQQQkbtZXnTz YwiCQ1BD690jwrghzmxv6gufKFS9bSOLE19Q8pbHlIzmcNp25/y3IIJopa1UYMQMrplu G4QQJD0LL2bRjsYIhUICprxXl3oYk9y4ALEf5NBmvPOPbWxJlT97UOi+VBOYLFEt8gXS vYNDsf0duYye2I35QfQatpcBvVJKQTyQCQ3VCdUA74UDM5NirEOzBuF7a70ReCZpc/85 O1Pw== X-Received: by 10.66.248.227 with SMTP id yp3mr24478315pac.158.1364905203444; Tue, 02 Apr 2013 05:20:03 -0700 (PDT) Received: from localhost.localdomain (174-31-195-141.tukw.qwest.net. [174.31.195.141]) by mx.google.com with ESMTPS id f4sm1596359pbc.6.2013.04.02.05.20.02 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 02 Apr 2013 05:20:02 -0700 (PDT) From: Trent Piepho To: linux-arm-kernel@lists.infradead.org, spi-devel-general@lists.sourceforge.net Subject: [PATCH V2 04/12] spi/mxs: Fix extra CS pulses and read mode in multi-transfer messages Date: Tue, 2 Apr 2013 05:19:47 -0700 Message-Id: <1364905195-24286-4-git-send-email-tpiepho@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1364905195-24286-1-git-send-email-tpiepho@gmail.com> References: <1364905195-24286-1-git-send-email-tpiepho@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130402_082004_935015_F1D0B635 X-CRM114-Status: GOOD ( 14.43 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (tpiepho[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Marek Vasut , Fabio Estevam , Trent Piepho , Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org There are two bits which control the CS line in the CTRL0 register: LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS in SPI mode. Setting DEASSERT_CS causes CS to be de-asserted at the end of the transfer. It would normally be set on the final segment of the final transfer. The DMA code explicitly sets it in this case, but because it never clears the bit from the ctrl0 register is will remain set for all transfers in subsequent messages. This results in a CS pulse between transfers. There is a similar problem with the read mode bit never being cleared in DMA mode. This patch fixes DEASSERT_CS and READ being left on in DMA mode. Signed-off-by: Trent Piepho Cc: Marek Vasut Cc: Fabio Estevam Cc: Shawn Guo --- drivers/spi/spi-mxs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c index 3064304..86a714b 100644 --- a/drivers/spi/spi-mxs.c +++ b/drivers/spi/spi-mxs.c @@ -230,7 +230,8 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs, INIT_COMPLETION(spi->c); ctrl0 = readl(ssp->base + HW_SSP_CTRL0); - ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT; + ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC | + BM_SSP_CTRL0_READ); ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs); if (!(flags & TXRX_WRITE))