From patchwork Fri Apr 12 22:54:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 2438961 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 5D379DF2A1 for ; Fri, 12 Apr 2013 22:56:28 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UQmsm-0005jk-Kj; Fri, 12 Apr 2013 22:55:49 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UQmsX-0005nc-HQ; Fri, 12 Apr 2013 22:55:33 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UQms2-0005kR-9g for linux-arm-kernel@lists.infradead.org; Fri, 12 Apr 2013 22:55:04 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r3CMsurL020026; Fri, 12 Apr 2013 17:54:56 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r3CMsuLY001921; Fri, 12 Apr 2013 17:54:56 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Fri, 12 Apr 2013 17:54:56 -0500 Received: from localhost (kahuna.am.dhcp.ti.com [128.247.75.12]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r3CMsu2G003876; Fri, 12 Apr 2013 17:54:56 -0500 From: Nishanth Menon To: Subject: [PATCH V4 3/6] ARM: dts: OMAP4: add clock nodes for CPU Date: Fri, 12 Apr 2013 17:54:35 -0500 Message-ID: <1365807278-554-4-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1365807278-554-1-git-send-email-nm@ti.com> References: <1365807278-554-1-git-send-email-nm@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130412_185502_576189_AD78E130 X-CRM114-Status: UNSURE ( 8.22 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -9.3 (---------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-9.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.40 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -2.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Nishanth Menon , Paul Walmsley , Mike Turquette , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Tony Lindgren , devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Kevin Hilman , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org OMAP443x, OMAP446x and OMAP447x platforms use dpll_mpu clock. Add same to common definition. Cc: Benoit Cousson Signed-off-by: Nishanth Menon --- RFC of this patch approach for OMAP3 was discussed in http://marc.info/?t=136370325600009&r=1&w=2 along with the detailed context as to why this is an intermediate step. previous revisions of cpufreq-cpu0 support do not use this approach. [Probably belongs to Benoit's tree] arch/arm/boot/dts/omap4.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2a56428..1c6d969 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -31,6 +31,8 @@ cpu@0 { compatible = "arm,cortex-a9"; next-level-cache = <&L2>; + clocks = <&dpll_mpu>; + clock-names = "cpu"; }; cpu@1 { compatible = "arm,cortex-a9"; @@ -106,6 +108,11 @@ ti,hwmods = "counter_32k"; }; + dpll_mpu: dpll_mpu { + #clock-cells = <0>; + compatible = "ti,omap-clock"; + }; + omap4_pmx_core: pinmux@4a100040 { compatible = "ti,omap4-padconf", "pinctrl-single"; reg = <0x4a100040 0x0196>;