From patchwork Fri Apr 12 22:54:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 2439001 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 3BF313FD1A for ; Fri, 12 Apr 2013 22:56:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UQmsz-0005pF-L7; Fri, 12 Apr 2013 22:56:02 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UQmsg-0005oA-N6; Fri, 12 Apr 2013 22:55:42 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UQms3-0005l2-Ha for linux-arm-kernel@lists.infradead.org; Fri, 12 Apr 2013 22:55:08 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r3CMsxdJ029479; Fri, 12 Apr 2013 17:54:59 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r3CMsx8P001959; Fri, 12 Apr 2013 17:54:59 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Fri, 12 Apr 2013 17:54:58 -0500 Received: from localhost (kahuna.am.dhcp.ti.com [128.247.75.12]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r3CMswcU003885; Fri, 12 Apr 2013 17:54:58 -0500 From: Nishanth Menon To: Subject: [PATCH V4 4/6] ARM: dts: AM33XX: add clock nodes for CPU Date: Fri, 12 Apr 2013 17:54:36 -0500 Message-ID: <1365807278-554-5-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1365807278-554-1-git-send-email-nm@ti.com> References: <1365807278-554-1-git-send-email-nm@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130412_185503_816159_D6B4A4B7 X-CRM114-Status: GOOD ( 11.61 ) X-Spam-Score: -9.3 (---------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-9.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -2.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Nishanth Menon , Paul Walmsley , Mike Turquette , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Tony Lindgren , devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Kevin Hilman , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org AM33XX based platforms use dpll_mpu clock. Add same to common dtsi and remove the dummy clock node entry as AM33XX platform supports only device tree based boot. Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Tony Lindgren Signed-off-by: Nishanth Menon --- RFC of this patch was discussed in http://marc.info/?t=136370325600009&r=1&w=2 along with the detailed context as to why this is an intermediate step. previous revisions of cpufreq-cpu0 support do not use this approach. [Probably belongs to Benoit/Tony/Paul tree?] arch/arm/boot/dts/am33xx.dtsi | 7 +++++++ arch/arm/mach-omap2/cclock33xx_data.c | 1 - 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index df62830..3aed044 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -42,6 +42,8 @@ 275000 1125000 >; voltage-tolerance = <2>; /* 2 percentage */ + clocks = <&dpll_mpu>; + clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; @@ -89,6 +91,11 @@ reg = <0x48200000 0x1000>; }; + dpll_mpu: dpll_mpu { + #clock-cells = <0>; + compatible = "ti,omap-clock"; + }; + gpio0: gpio@44e07000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio1"; diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 7f091c8..8be6832 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -852,7 +852,6 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), - CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),