From patchwork Tue Apr 16 17:09:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 2450091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 1545CDF230 for ; Tue, 16 Apr 2013 17:10:01 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1US9OJ-0002hP-P4; Tue, 16 Apr 2013 17:09:59 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1US9OG-00032b-RD; Tue, 16 Apr 2013 17:09:56 +0000 Received: from avon.wwwdotorg.org ([2001:470:1f0f:bd7::2]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1US9OE-00032I-EV for linux-arm-kernel@lists.infradead.org; Tue, 16 Apr 2013 17:09:55 +0000 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id C71D16356; Tue, 16 Apr 2013 11:11:54 -0600 (MDT) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 8B44EE40F4; Tue, 16 Apr 2013 11:09:14 -0600 (MDT) From: Stephen Warren To: arm@kernel.org Subject: [PATCH] ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled Date: Tue, 16 Apr 2013 11:09:09 -0600 Message-Id: <1366132149-17294-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.10.4 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.97.7 at avon.wwwdotorg.org X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130416_130954_525483_72C5710D X-CRM114-Status: GOOD ( 11.56 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, Dave Martin , Stephen Warren , linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren When building the kernel with CONFIG_THUMB2_KERNEL enabled, older assemblers may emit the following error: reset-handler.S:78: Error: invalid immediate for address calculation (value = 0x00000004) Using an explicit adr.w instruction will solve this. Newer assemblers do this automatically. Use the W() macro to do this under Thumb mode only. Inspired-by: Joseph Lo Suggested-by: Dave Martin Signed-off-by: Stephen Warren --- Olof, Arnd, Can you please apply this directly to arm-soc. Thanks. This patch replaces patch 3/3 "ARM: tegra: make sure the pointer on 4 byte align when THUMB2_KERNEL enabled" which I forwarded yesterday. It can be applied to wherever Tegra's for-3.10/fixes branch was applied, and doesn't cause any conflicts/merge-issues with any other Tegra patches this cycle. arch/arm/mach-tegra/sleep.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 4ffae54..bb308ea 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -92,7 +92,7 @@ #ifdef CONFIG_CACHE_L2X0 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs - adr \tmp1, \phys_l2x0_saved_regs + W(adr) \tmp1, \phys_l2x0_saved_regs ldr \tmp1, [\tmp1] ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] ldr \tmp3, [\tmp2, #L2X0_CTRL]