From patchwork Tue Apr 23 23:55:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sherman Yin X-Patchwork-Id: 2481551 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id A175B3FD1A for ; Tue, 23 Apr 2013 23:57:56 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UUn5t-00047U-Om; Tue, 23 Apr 2013 23:57:53 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UUn5q-0005vh-Sf; Tue, 23 Apr 2013 23:57:50 +0000 Received: from mms3.broadcom.com ([216.31.210.19]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UUn5n-0005vN-UE for linux-arm-kernel@lists.infradead.org; Tue, 23 Apr 2013 23:57:48 +0000 Received: from [10.9.208.57] by mms3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 23 Apr 2013 16:49:31 -0700 X-Server-Uuid: B86B6450-0931-4310-942E-F00ED04CA7AF Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.1.438.0; Tue, 23 Apr 2013 16:55:54 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.1.438.0; Tue, 23 Apr 2013 16:55:54 -0700 Received: from ltrmn-lnxub75-vm (testboard-syin2.ric.broadcom.com [10.136.4.120]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 517DE39289; Tue, 23 Apr 2013 16:55:54 -0700 (PDT) Received: by ltrmn-lnxub75-vm (Postfix, from userid 35077) id F352B60774; Tue, 23 Apr 2013 16:55:49 -0700 (PDT) From: "Sherman Yin" To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2] ARM: Fix l2x0_init log message Date: Tue, 23 Apr 2013 16:55:40 -0700 Message-ID: <1366761340-6550-1-git-send-email-syin@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <5ddc968feee3af6c462b24ca53eeeb11bbb7b7a3> References: <5ddc968feee3af6c462b24ca53eeeb11bbb7b7a3> MIME-Version: 1.0 X-WSS-ID: 7D69C1812L83929028-10-01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130423_195748_155182_3D1C7A34 X-CRM114-Status: GOOD ( 13.36 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [216.31.210.19 listed in list.dnswl.org] -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: csd@broadcom.com, Sherman Yin , linus.walleij@linaro.org, mmayer@broadcom.com, swarren@wwwdotorg.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In the log at the end of l2x0_init(), "ways" and "l2x0_size" should be derived from the most recently read value from the AUX register. Previously, these were derived from the earlier value of the AUX register with modifications by the function paramters aux_val and aux_mask. Signed-off-by: Sherman Yin --- v2: Corrected switch statement arch/arm/mm/cache-l2x0.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index c465fac..ca50099 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -376,14 +376,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) l2x0_way_mask = (1 << ways) - 1; /* - * L2 cache Size = Way size * Number of ways - */ - way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; - way_size = 1 << (way_size + way_size_shift); - - l2x0_size = ways * way_size * SZ_1K; - - /* * Check if l2x0 controller is already enabled. * If you are booting from non-secure mode * accessing the below registers will fault. @@ -417,6 +409,37 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) outer_cache.disable = l2x0_disable; } + /* Update number of ways based on aux ctrl register value */ + switch (cache_id & L2X0_CACHE_ID_PART_MASK) { + case L2X0_CACHE_ID_PART_L310: + if (aux & (1 << 16)) + ways = 16; + else + ways = 8; + break; + case L2X0_CACHE_ID_PART_L210: + ways = (aux >> 13) & 0xf; + break; + + case AURORA_CACHE_ID: + ways = (aux >> 13) & 0xf; + ways = 2 << ((ways + 1) >> 2); + way_size_shift = AURORA_WAY_SIZE_SHIFT; + break; + default: + /* Assume unknown chips have 8 ways */ + ways = 8; + break; + } + + /* + * L2 cache Size = Way size * Number of ways + */ + way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; + way_size = 1 << (way_size + way_size_shift); + + l2x0_size = ways * way_size * SZ_1K; + printk(KERN_INFO "%s cache controller enabled\n", type); printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", ways, cache_id, aux, l2x0_size);