From patchwork Tue Apr 30 18:38:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Daudt X-Patchwork-Id: 2505931 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 2E1B6DFB75 for ; Tue, 30 Apr 2013 18:39:56 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UXFSs-00039j-IO; Tue, 30 Apr 2013 18:39:46 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UXFSp-0000aS-TW; Tue, 30 Apr 2013 18:39:43 +0000 Received: from mms1.broadcom.com ([216.31.210.17]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UXFSn-0000Zs-Ah for linux-arm-kernel@lists.infradead.org; Tue, 30 Apr 2013 18:39:42 +0000 Received: from [10.9.208.55] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.5)); Tue, 30 Apr 2013 11:35:38 -0700 X-Server-Uuid: 06151B78-6688-425E-9DE2-57CB27892261 Received: from IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) by IRVEXCHCAS07.corp.ad.broadcom.com (10.9.208.55) with Microsoft SMTP Server (TLS) id 14.1.438.0; Tue, 30 Apr 2013 11:39:08 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) with Microsoft SMTP Server id 14.1.438.0; Tue, 30 Apr 2013 11:39:08 -0700 Received: from mothra.ric.broadcom.com (test-csd10.ric.broadcom.com [10.136.18.149]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 4C478392AF; Tue, 30 Apr 2013 11:39:07 -0700 (PDT) From: "Christian Daudt" To: "Russell King" , "John Stultz" , "Thomas Gleixner" , "Olof Johansson" , "Arnd Bergmann" , "Stephen Warren" , "Will Deacon" Subject: [PATCH] ARM: bcm281xx: Add L2 support for Rev A2 chips Date: Tue, 30 Apr 2013 11:38:09 -0700 Message-ID: <1367347089-23788-1-git-send-email-csd@broadcom.com> X-Mailer: git-send-email 1.7.10.4 MIME-Version: 1.0 X-WSS-ID: 7D9ED17031W13071248-01-01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130430_143941_548675_F202280B X-CRM114-Status: GOOD ( 22.45 ) X-Spam-Score: -6.7 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [216.31.210.17 listed in list.dnswl.org] -2.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 T_HDRS_LCASE Odd capitalization of message header Cc: Josh Cartwright , Yehuda Yitschak , linux-doc@vger.kernel.org, Christian Daudt , devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Rob Herring , csd_b@daudt.org, "arm@kernel.org" , John Stultz , Rob Landley , Gregory CLEMENT , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Rev A2 SoCs have an unorthodox memory re-mapping and this needs to be reflected in the cache operations. This patch adds new outer cache functions for the l2x0 driver to support this SoC revision. It also adds a new compatible value for the cache to enable this functionality. Signed-off-by: Christian Daudt diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index cbef09b..69ddf9f 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -16,6 +16,9 @@ Required properties: performs the same operation). "marvell,"aurora-outer-cache: Marvell Controller designed to be compatible with the ARM one with outer cache mode. + "bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an + offset needs to be added to the address before passing down to the L2 + cache controller - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 41b2c6c..5e48c85 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -47,10 +47,10 @@ }; L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x3ff20000 0x1000>; - cache-unified; - cache-level = <2>; + compatible = "bcm,bcm11351-a2-pl310-cache"; + reg = <0x3ff20000 0x1000>; + cache-unified; + cache-level = <2>; }; timer@35006000 { diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index c465fac..6edba13 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -523,6 +523,162 @@ static void aurora_flush_range(unsigned long start, unsigned long end) } } +/* + * For certain Broadcom SoCs, depending on the address range, different offsets + * need to be added to the address before passing it to L2 for + * invalidation/clean/flush + * + * Section Address Range Offset EMI + * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC + * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS + * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC + * + * When the start and end addresses have crossed two different sections, we + * need to break the L2 operation into two, each within its own section. + * For example, if we need to invalidate addresses starts at 0xBFFF0000 and + * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) + * 0xC0000000 - 0xC0001000 + * + * Note 1: + * By breaking a single L2 operation into two, we may potentially suffer some + * performance hit, but keep in mind the cross section case is very rare + * + * Note 2: + * We do not need to handle the case when the start address is in + * Section 1 and the end address is in Section 3, since it is not a valid use + * case + */ + +#define BCM_VC_EMI_SEC1_START_ADDR 0x00000000UL +#define BCM_VC_EMI_SEC1_END_ADDR 0x3FFFFFFFUL +#define BCM_SYS_EMI_START_ADDR 0x40000000UL +#define BCM_SYS_EMI_END_ADDR 0xBFFFFFFFUL +#define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL +#define BCM_VC_EMI_SEC3_END_ADDR 0xFFFFFFFFUL + +#define BCM_SYS_EMI_OFFSET 0x40000000UL +#define BCM_VC_EMI_OFFSET 0x80000000UL + +static inline int bcm_addr_is_sys_emi(unsigned long addr) +{ + return (addr >= BCM_SYS_EMI_START_ADDR) && + (addr <= BCM_SYS_EMI_END_ADDR); +} + +static inline unsigned long bcm_l2_phys_addr(unsigned long addr) +{ + if (bcm_addr_is_sys_emi(addr)) + return addr + BCM_SYS_EMI_OFFSET; + else + return addr + BCM_VC_EMI_OFFSET; +} + +static void bcm_inv_range(unsigned long start, unsigned long end) +{ + unsigned long new_start, new_end; + + if (unlikely(end <= start)) + return; + + new_start = bcm_l2_phys_addr(start); + new_end = bcm_l2_phys_addr(end); + + /* normal case, no cross section between start and end */ + if (likely((bcm_addr_is_sys_emi(start) && bcm_addr_is_sys_emi(end)) || + (!bcm_addr_is_sys_emi(start) && !bcm_addr_is_sys_emi(end)))) { + l2x0_inv_range(new_start, new_end); + return; + } + + if (bcm_addr_is_sys_emi(start)) { + /* start address in Section 2. end address in Section 3 */ + l2x0_inv_range(new_start, + bcm_l2_phys_addr(BCM_SYS_EMI_END_ADDR)); + l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), + new_end); + } else { + /* start address in Section 1. end address in Section 2 */ + l2x0_inv_range(new_start, + bcm_l2_phys_addr(BCM_VC_EMI_SEC1_END_ADDR)); + l2x0_inv_range(bcm_l2_phys_addr(BCM_SYS_EMI_START_ADDR), + new_end); + } +} + +static void bcm_clean_range(unsigned long start, unsigned long end) +{ + unsigned long new_start, new_end; + + if (unlikely(end <= start)) + return; + + if ((end - start) >= l2x0_size) { + l2x0_clean_all(); + return; + } + + new_start = bcm_l2_phys_addr(start); + new_end = bcm_l2_phys_addr(end); + + /* normal case, no cross section between start and end */ + if (likely((bcm_addr_is_sys_emi(start) && bcm_addr_is_sys_emi(end)) || + (!bcm_addr_is_sys_emi(start) && !bcm_addr_is_sys_emi(end)))) { + l2x0_clean_range(new_start, new_end); + return; + } + + if (bcm_addr_is_sys_emi(start)) { + /* start address in Section 2. end address in Section 3 */ + l2x0_clean_range(new_start, + bcm_l2_phys_addr(BCM_SYS_EMI_END_ADDR)); + l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), + new_end); + } else { + /* start address in Section 1. end address in Section 2 */ + l2x0_clean_range(new_start, + bcm_l2_phys_addr(BCM_VC_EMI_SEC1_END_ADDR)); + l2x0_clean_range(bcm_l2_phys_addr(BCM_SYS_EMI_START_ADDR), + new_end); + } +} + +static void bcm_flush_range(unsigned long start, unsigned long end) +{ + unsigned long new_start, new_end; + + if (unlikely(end <= start)) + return; + + if ((end - start) >= l2x0_size) { + l2x0_flush_all(); + return; + } + + new_start = bcm_l2_phys_addr(start); + new_end = bcm_l2_phys_addr(end); + + /* normal case, no cross section between start and end */ + if (likely((bcm_addr_is_sys_emi(start) && bcm_addr_is_sys_emi(end)) || + (!bcm_addr_is_sys_emi(start) && !bcm_addr_is_sys_emi(end)))) { + l2x0_flush_range(new_start, new_end); + return; + } + + if (bcm_addr_is_sys_emi(start)) { + /* start address in Section 2. end address in Section 3 */ + l2x0_flush_range(new_start, + bcm_l2_phys_addr(BCM_SYS_EMI_END_ADDR)); + l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), + new_end); + } else { + /* start address in Section 1. end address in Section 2 */ + l2x0_flush_range(new_start, + bcm_l2_phys_addr(BCM_VC_EMI_SEC1_END_ADDR)); + l2x0_flush_range(bcm_l2_phys_addr(BCM_SYS_EMI_START_ADDR), + new_end); + } +} + static void __init l2x0_of_setup(const struct device_node *np, u32 *aux_val, u32 *aux_mask) { @@ -765,6 +921,21 @@ static const struct l2x0_of_data aurora_no_outer_data = { }, }; +static const struct l2x0_of_data bcm_l2x0_data = { + .setup = pl310_of_setup, + .save = pl310_save, + .outer_cache = { + .resume = pl310_resume, + .inv_range = bcm_inv_range, + .clean_range = bcm_clean_range, + .flush_range = bcm_flush_range, + .sync = l2x0_cache_sync, + .flush_all = l2x0_flush_all, + .inv_all = l2x0_inv_all, + .disable = l2x0_disable, + }, +}; + static const struct of_device_id l2x0_ids[] __initconst = { { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data }, { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data }, @@ -773,6 +944,8 @@ static const struct of_device_id l2x0_ids[] __initconst = { .data = (void *)&aurora_no_outer_data}, { .compatible = "marvell,aurora-outer-cache", .data = (void *)&aurora_with_outer_data}, + { .compatible = "bcm,bcm11351-a2-pl310-cache", + .data = (void *)&bcm_l2x0_data}, {} };