From patchwork Wed May 8 19:06:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 2541381 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 59FD93FE1F for ; Wed, 8 May 2013 19:08:47 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ua9iV-0008QZ-TS; Wed, 08 May 2013 19:07:56 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ua9i7-0000fx-Nm; Wed, 08 May 2013 19:07:31 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ua9hS-0000Zw-Ut for linux-arm-kernel@lists.infradead.org; Wed, 08 May 2013 19:06:56 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r48J6Lox030452; Wed, 8 May 2013 14:06:22 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r48J6LJF004255; Wed, 8 May 2013 14:06:21 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Wed, 8 May 2013 14:06:21 -0500 Received: from localhost (kahuna.am.dhcp.ti.com [128.247.91.59]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r48J6Lq6015632; Wed, 8 May 2013 14:06:21 -0500 From: Nishanth Menon To: Benoit Cousson , Tony Lindgren , Kevin Hilman , Mike Turquette Subject: [PATCH V5 4/6] ARM: dts: AM33XX: add clock nodes for CPU Date: Wed, 8 May 2013 14:06:14 -0500 Message-ID: <1368039976-29648-5-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1368039976-29648-1-git-send-email-nm@ti.com> References: <1368039976-29648-1-git-send-email-nm@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130508_150651_173695_5D6A5C0F X-CRM114-Status: GOOD ( 11.67 ) X-Spam-Score: -8.3 (--------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-8.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Nishanth Menon , Paul Walmsley , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org AM33XX based platforms use dpll_mpu clock. Add same to common dtsi and remove the dummy clock node entry as AM33XX platform supports only device tree based boot. Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Tony Lindgren Signed-off-by: Nishanth Menon --- Change in this revision from previous: - rebase, no functional change. Previous version: http://marc.info/?l=linux-kernel&m=136580755324232&w=2 arch/arm/boot/dts/am33xx.dtsi | 7 +++++++ arch/arm/mach-omap2/cclock33xx_data.c | 1 - 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index d110110..27f6eb1 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -42,6 +42,8 @@ 275000 1125000 >; voltage-tolerance = <2>; /* 2 percentage */ + clocks = <&dpll_mpu>; + clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; @@ -89,6 +91,11 @@ reg = <0x48200000 0x1000>; }; + dpll_mpu: dpll_mpu { + #clock-cells = <0>; + compatible = "ti,omap-clock"; + }; + gpio0: gpio@44e07000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio1"; diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 6ebc780..4e39171 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -860,7 +860,6 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck), CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck), CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), - CLK("cpu0", NULL, &dpll_mpu_ck), CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck), CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),