From patchwork Thu May 9 11:40:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: PranavkumarSawargaonkar X-Patchwork-Id: 2543871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 8A9E33FD4E for ; Thu, 9 May 2013 11:41:51 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UaPED-0005jG-75; Thu, 09 May 2013 11:41:41 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UaPEA-0003c9-DT; Thu, 09 May 2013 11:41:38 +0000 Received: from mail-pa0-f48.google.com ([209.85.220.48]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UaPE7-0003bk-8V for linux-arm-kernel@lists.infradead.org; Thu, 09 May 2013 11:41:36 +0000 Received: by mail-pa0-f48.google.com with SMTP id kp6so2042856pab.7 for ; Thu, 09 May 2013 04:41:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=8hUhkkdvyZ+DIz7bn4Or0I6Vt5mb+ptNtWK4VEAs29U=; b=CqP9Anzqs7L8lA8ECIDzWHZ8uoYalfbA8hpCsTA0pTuohFwBURJ+iT2I9MytlS+weT jCtTyjVWW4pea0ZOCblMluFF90uEsYrEK4h2hx2ycdbhIBJUsoSq5TUoOSOfZHx9Ry5q vED8QyNCGAfNO82a2xeYy+wU+ucU0gCraUuDyVf8HCvKcqtKcJF7DPFL1Tq2uapAp8Sa lfcBrccFdvCOMxu4cQSHnCn9ntGhLVvbID+Q8aN0C+lWlWpiS3MPZ2Kc7PYOiYoNyrCz QGrsxc0WYb0H7Jh924g9jrGM4eqsDeU86rJT3yj9/iM+GjLNCgq7a4n8IdKtFjKaaf7e N3kQ== X-Received: by 10.66.9.99 with SMTP id y3mr12617129paa.189.1368099670268; Thu, 09 May 2013 04:41:10 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.72.18.82]) by mx.google.com with ESMTPSA id vv6sm3401274pab.6.2013.05.09.04.41.06 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 04:41:09 -0700 (PDT) From: Pranavkumar Sawargaonkar To: kvmarm@lists.cs.columbia.edu Subject: [PATCH] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits Date: Thu, 9 May 2013 17:10:11 +0530 Message-Id: <1368099611-4738-1-git-send-email-pranavkumar@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQlR+5eRMSnsJjb2uZPJDiosQKG+3+Ee+ZufZd8YAMBbuEvsOrXEDyXxAtqoLECNEBVHOXZi X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130509_074135_367812_7C712A30 X-CRM114-Status: UNSURE ( 8.36 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.48 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linaro-kernel@lists.linaro.org, Anup Patel , patches@linaro.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, Pranavkumar Sawargaonkar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch does following fixes: 1. Make HCR_* flags as unsigned long long constants Reason : By default, compiler assumes numeric constants as signed hence sign extending it when assigned to unsigned variable such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and HCR_CD making entire guest memory non-cacheable. On real HW, this breaks Stage2 ttbl walks and also breaks VirtIO. 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Anup Patel --- arch/arm64/include/asm/kvm_arm.h | 73 +++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 36 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 8ced0ca..0a951db 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -18,44 +18,45 @@ #ifndef __ARM64_KVM_ARM_H__ #define __ARM64_KVM_ARM_H__ +#include #include /* Hyp Configuration Register (HCR) bits */ -#define HCR_ID (1 << 33) -#define HCR_CD (1 << 32) +#define HCR_ID (_AC(0x1, ULL) << 33) +#define HCR_CD (_AC(0x1, ULL) << 32) #define HCR_RW_SHIFT 31 -#define HCR_RW (1 << HCR_RW_SHIFT) -#define HCR_TRVM (1 << 30) -#define HCR_HCD (1 << 29) -#define HCR_TDZ (1 << 28) -#define HCR_TGE (1 << 27) -#define HCR_TVM (1 << 26) -#define HCR_TTLB (1 << 25) -#define HCR_TPU (1 << 24) -#define HCR_TPC (1 << 23) -#define HCR_TSW (1 << 22) -#define HCR_TAC (1 << 21) -#define HCR_TIDCP (1 << 20) -#define HCR_TSC (1 << 19) -#define HCR_TID3 (1 << 18) -#define HCR_TID2 (1 << 17) -#define HCR_TID1 (1 << 16) -#define HCR_TID0 (1 << 15) -#define HCR_TWE (1 << 14) -#define HCR_TWI (1 << 13) -#define HCR_DC (1 << 12) -#define HCR_BSU (3 << 10) -#define HCR_BSU_IS (1 << 10) -#define HCR_FB (1 << 9) -#define HCR_VA (1 << 8) -#define HCR_VI (1 << 7) -#define HCR_VF (1 << 6) -#define HCR_AMO (1 << 5) -#define HCR_IMO (1 << 4) -#define HCR_FMO (1 << 3) -#define HCR_PTW (1 << 2) -#define HCR_SWIO (1 << 1) -#define HCR_VM (1) +#define HCR_RW (_AC(0x1, ULL) << HCR_RW_SHIFT) +#define HCR_TRVM (_AC(0x1, ULL) << 30) +#define HCR_HCD (_AC(0x1, ULL) << 29) +#define HCR_TDZ (_AC(0x1, ULL) << 28) +#define HCR_TGE (_AC(0x1, ULL) << 27) +#define HCR_TVM (_AC(0x1, ULL) << 26) +#define HCR_TTLB (_AC(0x1, ULL) << 25) +#define HCR_TPU (_AC(0x1, ULL) << 24) +#define HCR_TPC (_AC(0x1, ULL) << 23) +#define HCR_TSW (_AC(0x1, ULL) << 22) +#define HCR_TAC (_AC(0x1, ULL) << 21) +#define HCR_TIDCP (_AC(0x1, ULL) << 20) +#define HCR_TSC (_AC(0x1, ULL) << 19) +#define HCR_TID3 (_AC(0x1, ULL) << 18) +#define HCR_TID2 (_AC(0x1, ULL) << 17) +#define HCR_TID1 (_AC(0x1, ULL) << 16) +#define HCR_TID0 (_AC(0x1, ULL) << 15) +#define HCR_TWE (_AC(0x1, ULL) << 14) +#define HCR_TWI (_AC(0x1, ULL) << 13) +#define HCR_DC (_AC(0x1, ULL) << 12) +#define HCR_BSU (_AC(0x3, ULL) << 10) +#define HCR_BSU_IS (_AC(0x1, ULL) << 10) +#define HCR_FB (_AC(0x1, ULL) << 9) +#define HCR_VA (_AC(0x1, ULL) << 8) +#define HCR_VI (_AC(0x1, ULL) << 7) +#define HCR_VF (_AC(0x1, ULL) << 6) +#define HCR_AMO (_AC(0x1, ULL) << 5) +#define HCR_IMO (_AC(0x1, ULL) << 4) +#define HCR_FMO (_AC(0x1, ULL) << 3) +#define HCR_PTW (_AC(0x1, ULL) << 2) +#define HCR_SWIO (_AC(0x1, ULL) << 1) +#define HCR_VM (_AC(0x1, ULL)) /* * The bits we set in HCR: @@ -111,9 +112,9 @@ #define VTCR_EL2_SH0_MASK (3 << 12) #define VTCR_EL2_SH0_INNER (3 << 12) #define VTCR_EL2_ORGN0_MASK (3 << 10) -#define VTCR_EL2_ORGN0_WBWA (3 << 10) +#define VTCR_EL2_ORGN0_WBWA (1 << 10) #define VTCR_EL2_IRGN0_MASK (3 << 8) -#define VTCR_EL2_IRGN0_WBWA (3 << 8) +#define VTCR_EL2_IRGN0_WBWA (1 << 8) #define VTCR_EL2_SL0_MASK (3 << 6) #define VTCR_EL2_SL0_LVL1 (1 << 6) #define VTCR_EL2_T0SZ_MASK 0x3f