From patchwork Fri May 10 07:23:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: PranavkumarSawargaonkar X-Patchwork-Id: 2548491 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 042DA3FD85 for ; Fri, 10 May 2013 07:25:21 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UahhR-0001LM-7D; Fri, 10 May 2013 07:25:05 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UahhI-0001IR-MT; Fri, 10 May 2013 07:24:56 +0000 Received: from mail-da0-x232.google.com ([2607:f8b0:400e:c00::232]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UahhG-0001G6-M1 for linux-arm-kernel@lists.infradead.org; Fri, 10 May 2013 07:24:55 +0000 Received: by mail-da0-f50.google.com with SMTP id i23so2080448dad.37 for ; Fri, 10 May 2013 00:24:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=vqXw54iWGVo6PIVa0avvdZfr/BIVcOiFfwRXbFHorYI=; b=E9neOBMzyDm9+YObXZLZJ7WblZD0MLDr1R35GJKGxtfJf0NVY5LK9RJR7eJNT/Kow4 9hHWoy5ofOeau/eT0eYyBskUh2ynhA31h9EG7w40d1yWXaeisNIIFXvFw0FjiCN/Zp8Q uY5IrFXW5eNvDXZ5VJnN9gUYsTWFhKD3KWLwFnE+TklZYZwv4TprT8uIQ19m5d7Ra8h+ EcThQZAvjqdGHAYkGyyBOljrELM0MH/QbPU9fW+04N0TTdOtRrGmGU3KhMocQYEI31Fy M6NkenrOCywdV8R/0NiwUbrytAhCzGU8L3XtB3w8LFWb4gLBZj/5s0tQTKgYryiwrrsU mYjg== X-Received: by 10.68.227.106 with SMTP id rz10mr16356925pbc.32.1368170672718; Fri, 10 May 2013 00:24:32 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.72.18.82]) by mx.google.com with ESMTPSA id al2sm1607309pbc.25.2013.05.10.00.24.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 May 2013 00:24:32 -0700 (PDT) From: Pranavkumar Sawargaonkar To: kvmarm@lists.cs.columbia.edu Subject: [PATCH V2] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits Date: Fri, 10 May 2013 12:53:50 +0530 Message-Id: <1368170630-19567-1-git-send-email-pranavkumar@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmJ/oarepPnJaBN+DtBhG/krJN0XIWAgVAqVgo0+cq/zevGgq1dzcVbs6+HqLLkRDPA1fDa X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130510_032454_795910_8CCA7152 X-CRM114-Status: UNSURE ( 8.45 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linaro-kernel@lists.linaro.org, Anup Patel , patches@linaro.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, Pranavkumar Sawargaonkar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch does following fixes: 1. Make HCR_* flags as unsigned long long constants Reason : By default, compiler assumes numeric constants as signed hence sign extending it when assigned to unsigned variable such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and HCR_CD making entire guest memory non-cacheable. On real HW, this breaks Stage2 ttbl walks and also breaks VirtIO. 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Anup Patel --- arch/arm64/include/asm/kvm_arm.h | 73 +++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 36 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 8ced0ca..14ead69 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -18,44 +18,45 @@ #ifndef __ARM64_KVM_ARM_H__ #define __ARM64_KVM_ARM_H__ +#include #include /* Hyp Configuration Register (HCR) bits */ -#define HCR_ID (1 << 33) -#define HCR_CD (1 << 32) +#define HCR_ID (UL(0x1) << 33) +#define HCR_CD (UL(0x1) << 32) #define HCR_RW_SHIFT 31 -#define HCR_RW (1 << HCR_RW_SHIFT) -#define HCR_TRVM (1 << 30) -#define HCR_HCD (1 << 29) -#define HCR_TDZ (1 << 28) -#define HCR_TGE (1 << 27) -#define HCR_TVM (1 << 26) -#define HCR_TTLB (1 << 25) -#define HCR_TPU (1 << 24) -#define HCR_TPC (1 << 23) -#define HCR_TSW (1 << 22) -#define HCR_TAC (1 << 21) -#define HCR_TIDCP (1 << 20) -#define HCR_TSC (1 << 19) -#define HCR_TID3 (1 << 18) -#define HCR_TID2 (1 << 17) -#define HCR_TID1 (1 << 16) -#define HCR_TID0 (1 << 15) -#define HCR_TWE (1 << 14) -#define HCR_TWI (1 << 13) -#define HCR_DC (1 << 12) -#define HCR_BSU (3 << 10) -#define HCR_BSU_IS (1 << 10) -#define HCR_FB (1 << 9) -#define HCR_VA (1 << 8) -#define HCR_VI (1 << 7) -#define HCR_VF (1 << 6) -#define HCR_AMO (1 << 5) -#define HCR_IMO (1 << 4) -#define HCR_FMO (1 << 3) -#define HCR_PTW (1 << 2) -#define HCR_SWIO (1 << 1) -#define HCR_VM (1) +#define HCR_RW (UL(0x1) << HCR_RW_SHIFT) +#define HCR_TRVM (UL(0x1) << 30) +#define HCR_HCD (UL(0x1) << 29) +#define HCR_TDZ (UL(0x1) << 28) +#define HCR_TGE (UL(0x1) << 27) +#define HCR_TVM (UL(0x1) << 26) +#define HCR_TTLB (UL(0x1) << 25) +#define HCR_TPU (UL(0x1) << 24) +#define HCR_TPC (UL(0x1) << 23) +#define HCR_TSW (UL(0x1) << 22) +#define HCR_TAC (UL(0x1) << 21) +#define HCR_TIDCP (UL(0x1) << 20) +#define HCR_TSC (UL(0x1) << 19) +#define HCR_TID3 (UL(0x1) << 18) +#define HCR_TID2 (UL(0x1) << 17) +#define HCR_TID1 (UL(0x1) << 16) +#define HCR_TID0 (UL(0x1) << 15) +#define HCR_TWE (UL(0x1) << 14) +#define HCR_TWI (UL(0x1) << 13) +#define HCR_DC (UL(0x1) << 12) +#define HCR_BSU (UL(0x3) << 10) +#define HCR_BSU_IS (UL(0x1) << 10) +#define HCR_FB (UL(0x1) << 9) +#define HCR_VA (UL(0x1) << 8) +#define HCR_VI (UL(0x1) << 7) +#define HCR_VF (UL(0x1) << 6) +#define HCR_AMO (UL(0x1) << 5) +#define HCR_IMO (UL(0x1) << 4) +#define HCR_FMO (UL(0x1) << 3) +#define HCR_PTW (UL(0x1) << 2) +#define HCR_SWIO (UL(0x1) << 1) +#define HCR_VM (UL(0x1)) /* * The bits we set in HCR: @@ -111,9 +112,9 @@ #define VTCR_EL2_SH0_MASK (3 << 12) #define VTCR_EL2_SH0_INNER (3 << 12) #define VTCR_EL2_ORGN0_MASK (3 << 10) -#define VTCR_EL2_ORGN0_WBWA (3 << 10) +#define VTCR_EL2_ORGN0_WBWA (1 << 10) #define VTCR_EL2_IRGN0_MASK (3 << 8) -#define VTCR_EL2_IRGN0_WBWA (3 << 8) +#define VTCR_EL2_IRGN0_WBWA (1 << 8) #define VTCR_EL2_SL0_MASK (3 << 6) #define VTCR_EL2_SL0_LVL1 (1 << 6) #define VTCR_EL2_T0SZ_MASK 0x3f