From patchwork Mon May 13 17:07:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 2559541 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 9087FDF2E5 for ; Mon, 13 May 2013 17:22:14 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UbwQ1-0007qN-9B; Mon, 13 May 2013 17:20:17 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UbwFt-0001rw-FS; Mon, 13 May 2013 17:09:45 +0000 Received: from smtp48.i.mail.ru ([94.100.177.108]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UbwEd-0001hC-Uc for linux-arm-kernel@lists.infradead.org; Mon, 13 May 2013 17:08:35 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=bhhuscDxJyvbBguvDi2Vv2Qp236w4CCY+bFGXoywax0=; b=kdnhFzT8kJI4xEqGCk43MaeJYb3LUCm0YdFN83kiSqZGm7d068/R4Q8+/yYSXyWsEL/7PXz48ryun729AL2mOUfe5DiSsS35xSPwF5T1JuG0yiyxDkbBLeqfVxR4/XDtpp/bEUYWHUEtjHk5+Hu/jb9khOOZiG9t5dW0UxiJsok=; Received: from [188.134.40.128] (port=6013 helo=shc.zet) by smtp48.i.mail.ru with esmtpa (envelope-from ) id 1UbwEJ-0000Vn-Ja; Mon, 13 May 2013 21:08:07 +0400 From: Alexander Shiyan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/15] ARM: clps711x: Add clocksource framework Date: Mon, 13 May 2013 21:07:32 +0400 Message-Id: <1368464857-5038-13-git-send-email-shc_work@mail.ru> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1368464857-5038-1-git-send-email-shc_work@mail.ru> References: <1368464857-5038-1-git-send-email-shc_work@mail.ru> X-Spam: Not detected X-Mras: Ok X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130513_130828_371919_E8F57848 X-CRM114-Status: GOOD ( 13.59 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (shc_work[at]mail.ru) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Olof Johansson , Russell King , Alexander Shiyan , Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Signed-off-by: Alexander Shiyan --- arch/arm/Kconfig | 1 + arch/arm/mach-clps711x/common.c | 48 ++++++++++++++++++++++++++++++++++------- 2 files changed, 41 insertions(+), 8 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 10cdfa9..2af27f7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -367,6 +367,7 @@ config ARCH_CLPS711X select ARCH_REQUIRE_GPIOLIB select AUTO_ZRELADDR select CLKDEV_LOOKUP + select CLKSRC_MMIO select COMMON_CLK select CPU_ARM720T select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 768d41c6..bd65839 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -27,12 +27,14 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include @@ -251,13 +253,32 @@ asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) handle_IRQ(fls16(irqstat) + 16, regs); } +static u32 notrace clps711x_sched_clock_read(void) +{ + return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D); +} + static void clps711x_clockevent_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { + disable_irq(IRQ_TC2OI); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + enable_irq(IRQ_TC2OI); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* Not supported */ + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } } static struct clock_event_device clockevent_clps711x = { - .name = "CLPS711x Clockevents", + .name = "clps711x-clockevent", .rating = 300, .features = CLOCK_EVT_FEAT_PERIODIC, .set_mode = clps711x_clockevent_set_mode, @@ -271,8 +292,8 @@ static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id) } static struct irqaction clps711x_timer_irq = { - .name = "CLPS711x Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .name = "clps711x-timer", + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = clps711x_timer_interrupt, }; @@ -320,9 +341,9 @@ void __init clps711x_timer_init(void) else timh = 541440; } else - timh = cpu / 144; + timh = DIV_ROUND_CLOSEST(cpu, 144); - timl = timh / 256; + timl = DIV_ROUND_CLOSEST(timh, 256); /* All clocks are fixed */ add_fixed_clk(clk_pll, "pll", pll); @@ -335,13 +356,24 @@ void __init clps711x_timer_init(void) pr_info("CPU frequency set at %i Hz.\n", cpu); + /* Start Timer1 in free running mode (Low frequency) */ + tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M); + clps_writel(tmp, SYSCON1); + + setup_sched_clock(clps711x_sched_clock_read, 16, timl); + + clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D, + "clps711x_clocksource", timl, 300, 16, + clocksource_mmio_readw_down); + + /* Set Timer2 prescaler */ clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D); - tmp = clps_readl(SYSCON1); - tmp |= SYSCON1_TC2S | SYSCON1_TC2M; + /* Start Timer2 in prescale mode (High frequency)*/ + tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S; clps_writel(tmp, SYSCON1); - clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff); + clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0); setup_irq(IRQ_TC2OI, &clps711x_timer_irq); }