From patchwork Tue May 14 09:26:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 2563661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 1EAF53FD85 for ; Tue, 14 May 2013 09:35:15 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UcBZ6-0001ia-Qs; Tue, 14 May 2013 09:30:42 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UcBX3-00012t-QV; Tue, 14 May 2013 09:28:29 +0000 Received: from mail-pb0-x235.google.com ([2607:f8b0:400e:c01::235]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UcBX0-00012T-FN for linux-arm-kernel@lists.infradead.org; Tue, 14 May 2013 09:28:27 +0000 Received: by mail-pb0-f53.google.com with SMTP id un1so263737pbc.26 for ; Tue, 14 May 2013 02:28:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=IrxLSYhVG/XywutG+A0RQI6Xz0DjUdSjY/VHiXumvXc=; b=b5ExBdGLo3mEIJsUbi4t/vTy3v/gCBFhSAAnDclD0ldspbqDRAtQ75rMwtQhn1dOZe TinGsomzbGJ6qLwNbNCuFxHaKWfOOURKf2kc81NbHkwHvjD0ZeAUMJlT60IrLmE5oigE uFKUjh4YETWCrFXAX2Qn16pReLjO00cQTrqcaYttO+E3MuYXGo99M7kMSd6HWZJNiKgH 9avoPQjWbfcdGOwwFoBNWuhY8jEm+TiwcxOehWjDIqJER8jUHLouY2TEXBqxkhuT/MYd CC603oUhYnV6+AOxCkebxytL07MC1pq+8eaq9MNeDP0l/ZehI+HRHw0dD89lAHw+RSwu AmJQ== X-Received: by 10.66.122.130 with SMTP id ls2mr16113162pab.128.1368523684803; Tue, 14 May 2013 02:28:04 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.72.18.82]) by mx.google.com with ESMTPSA id aj2sm17551506pbc.1.2013.05.14.02.28.01 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 14 May 2013 02:28:03 -0700 (PDT) From: Anup Patel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: mm: Fix operands of clz in __flush_dcache_all Date: Tue, 14 May 2013 14:56:54 +0530 Message-Id: <1368523614-22484-1-git-send-email-anup.patel@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQlhKEJzCfuyq59LXDP8R89oj+Hk1uVmPsEJMsIHdVYhsBeMisvA/TXk9y/qfLsel+3B5BLW X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130514_052826_593090_EDB7818B X-CRM114-Status: GOOD ( 10.24 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Sukanto Ghosh , Catalin Marinas , linaro-kernel@lists.linaro.org, Anup Patel , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Sukanto Ghosh The format of the lower 32-bits of the 64-bit operand to 'dc cisw' is unchanged from ARMv7 architecture and the upper bits are RES0. This implies that the 'way' field of the operand of 'dc cisw' occupies the bit-positions [31 .. (32-A)]. Due to the use of 64-bit extended operands to 'clz', the existing implementation of __flush_dcache_all is incorrectly placing the 'way' field in the bit-positions [63 .. (64-A)]. Signed-off-by: Sukanto Ghosh Tested-by: Anup Patel --- arch/arm64/mm/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index abe69b8..48a3860 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -52,7 +52,7 @@ loop1: add x2, x2, #4 // add 4 (line length offset) mov x4, #0x3ff and x4, x4, x1, lsr #3 // find maximum number on the way size - clz x5, x4 // find bit position of way size increment + clz w5, w4 // find bit position of way size increment mov x7, #0x7fff and x7, x7, x1, lsr #13 // extract max number of the index size loop2: