From patchwork Mon May 20 06:51:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: girishks2000@gmail.com X-Patchwork-Id: 2592781 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 25B053FE81 for ; Mon, 20 May 2013 13:11:26 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UePs5-0005nL-0m; Mon, 20 May 2013 13:11:25 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UeJxj-0005Yi-QC; Mon, 20 May 2013 06:52:51 +0000 Received: from mail-pb0-x22c.google.com ([2607:f8b0:400e:c01::22c]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UeJxN-0005UW-9M for linux-arm-kernel@lists.infradead.org; Mon, 20 May 2013 06:52:30 +0000 Received: by mail-pb0-f44.google.com with SMTP id wz12so811863pbc.17 for ; Sun, 19 May 2013 23:51:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=P1GoDt0YO4aLWm+SL1YkxMaoEJgUJhbNz3KDHWFeY3U=; b=LlrWhrsT+9ITSK9IE8tWbvBAHxyn+5Vqr7VMUE89JOPj5rGGMM50IofDnbX5RKxjPP na7eVVAq4QGq7jnMRQbOxtvqQmDCEqFX2M5Z+oG07OWx2s75yEaXWckQ7Tb0OBPbOX7H tD60lSMlq62uDqUy/W7m0uIE5pQa3rQyVeEw9KwNVfE7P82TShsBSBY9bUlpIBUciMHC pCYYgMEjqFP69nUYe2O5I5YiAc9I58Ys7UJw0z8VWc+RDV1JTaAtciRzlKe4HmuBiwsj dSYZdHqrFXAiSsxHUa7IRIHFKY+KcJE9owQueOGz6Nmf517FPhadBzXvycoHq2/ZJaJG bE1A== X-Received: by 10.68.212.72 with SMTP id ni8mr35350632pbc.114.1369032717041; Sun, 19 May 2013 23:51:57 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id nt2sm22842887pbc.17.2013.05.19.23.51.53 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 19 May 2013 23:51:56 -0700 (PDT) From: Girish K S To: spi-devel-general@lists.sourceforge.net, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 2/3] spi: s3c64xx: Added provision for dedicated cs pin Date: Mon, 20 May 2013 12:21:33 +0530 Message-Id: <1369032694-13183-3-git-send-email-ks.giri@samsung.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1369032694-13183-1-git-send-email-ks.giri@samsung.com> References: <1369032694-13183-1-git-send-email-ks.giri@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130520_025229_430733_C0094F4C X-CRM114-Status: GOOD ( 19.22 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (girishks2000[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (girishks2000[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: grant.likely@secretlab.ca, broonie@opensource.wolfsonmicro.com, Girish K S X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Girish K S The existing driver supports gpio based /cs signal. For controller's that have one device per controller, the slave device's /cs signal might be internally controlled by the chip select bit of slave select register. They are not externally asserted/deasserted using gpio pin. This patch adds support for controllers with dedicated /cs pin. if "cs-gpio" property doesnt exist in a spi dts node, the controller would treat the /cs pin as dedicated. Signed-off-by: Girish K S --- changes in v1: Added the missing data structure that caused the compilation error drivers/spi/spi-s3c64xx.c | 34 ++++++++++++++++++++++++++-------- 1 files changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 0a80692..eaf9e1c 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -208,6 +208,7 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; unsigned long gpios[4]; + bool cs_gpio; }; static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) @@ -570,14 +571,16 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ /* Deselect the last toggled device */ cs = sdd->tgl_spi->controller_data; - gpio_set_value(cs->line, - spi->mode & SPI_CS_HIGH ? 0 : 1); + if (sdd->cs_gpio) + gpio_set_value(cs->line, + spi->mode & SPI_CS_HIGH ? 0 : 1); } sdd->tgl_spi = NULL; } cs = spi->controller_data; - gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); + if (sdd->cs_gpio) + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); /* Start the signals */ writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); @@ -709,7 +712,8 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi == spi) sdd->tgl_spi = NULL; - gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); + if (sdd->cs_gpio) + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); /* Quiese the signals */ writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); @@ -997,8 +1001,10 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( { struct s3c64xx_spi_csinfo *cs; struct device_node *slave_np, *data_np = NULL; + struct s3c64xx_spi_driver_data *sdd; u32 fb_delay = 0; + sdd = spi_master_get_devdata(spi->master); slave_np = spi->dev.of_node; if (!slave_np) { dev_err(&spi->dev, "device node not found\n"); @@ -1018,7 +1024,10 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( return ERR_PTR(-ENOMEM); } - cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); + /* The CS line is asserted/deasserted by the gpio pin */ + if (sdd->cs_gpio) + cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); + if (!gpio_is_valid(cs->line)) { dev_err(&spi->dev, "chip select gpio is not specified or invalid\n"); kfree(cs); @@ -1058,7 +1067,8 @@ static int s3c64xx_spi_setup(struct spi_device *spi) return -ENODEV; } - if (!spi_get_ctldata(spi)) { + /* Request gpio only if cs line is asserted by gpio pins */ + if (sdd->cs_gpio) { err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH, dev_name(&spi->dev)); if (err) { @@ -1067,9 +1077,11 @@ static int s3c64xx_spi_setup(struct spi_device *spi) cs->line, err); goto err_gpio_req; } - spi_set_ctldata(spi, cs); } + if (!spi_get_ctldata(spi)) + spi_set_ctldata(spi, cs); + sci = sdd->cntrlr_info; spin_lock_irqsave(&sdd->lock, flags); @@ -1147,8 +1159,10 @@ err_gpio_req: static void s3c64xx_spi_cleanup(struct spi_device *spi) { struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); + struct s3c64xx_spi_driver_data *sdd; - if (cs) { + sdd = spi_master_get_devdata(spi->master); + if (cs && sdd->cs_gpio) { gpio_free(cs->line); if (spi->dev.of_node) kfree(cs); @@ -1325,7 +1339,11 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->cntrlr_info = sci; sdd->pdev = pdev; sdd->sfr_start = mem_res->start; + sdd->cs_gpio = false; if (pdev->dev.of_node) { + if (of_find_property(pdev->dev.of_node, "cs-gpio", NULL)) + sdd->cs_gpio = true; + ret = of_alias_get_id(pdev->dev.of_node, "spi"); if (ret < 0) { dev_err(&pdev->dev, "failed to get alias id, errno %d\n",