From patchwork Mon May 20 10:39:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 2593021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 0B4643FD4E for ; Mon, 20 May 2013 13:45:07 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UeQOf-0006Pr-PK; Mon, 20 May 2013 13:45:06 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UeNWH-0002PH-4m; Mon, 20 May 2013 10:40:45 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UeNVh-0002LN-Ku for linux-arm-kernel@lists.infradead.org; Mon, 20 May 2013 10:40:14 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Mon, 20 May 2013 03:46:19 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 20 May 2013 03:35:44 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 20 May 2013 03:35:44 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.298.1; Mon, 20 May 2013 03:39:45 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH V2 2/6] ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9 Date: Mon, 20 May 2013 18:39:25 +0800 Message-ID: <1369046369-12489-3-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.2.2 In-Reply-To: <1369046369-12489-1-git-send-email-josephl@nvidia.com> References: <1369046369-12489-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130520_064010_089370_9815BE2A X-CRM114-Status: UNSURE ( 8.70 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -8.0 (--------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-8.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -1.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org For supporting single image on all Tegra series, we need to skip some HW support code for Cortex-A9 only. Signed-off-by: Joseph Lo --- V2: * no change; but double confirmed the patch is OK with THUMB2_KERNEL --- arch/arm/mach-tegra/sleep.S | 8 +++++--- arch/arm/mach-tegra/sleep.h | 24 ++++++++++++++++++------ 2 files changed, 23 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 364d845..9daaef2 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu) isb #ifdef CONFIG_CACHE_L2X0 /* Disable L2 cache */ - mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000 - mov r5, #0 - str r5, [r4, #L2X0_CTRL] + check_cpu_part_num 0xc09, r9, r10 + movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) + movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) + moveq r5, #0 + streq r5, [r4, #L2X0_CTRL] #endif mov pc, r0 ENDPROC(tegra_shut_off_mmu) diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index f9f2164..2269c0d 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -70,19 +70,31 @@ movt \reg, #:upper16:\val .endm +/* Marco to check CPU part num */ +.macro check_cpu_part_num part_num, tmp1, tmp2 + mrc p15, 0, \tmp1, c0, c0, 0 + ubfx \tmp1, \tmp1, #4, #12 + mov32 \tmp2, \part_num + cmp \tmp1, \tmp2 +.endm + /* Macro to exit SMP coherency. */ .macro exit_smp, tmp1, tmp2 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR isb - cpu_id \tmp1 - mov \tmp1, \tmp1, lsl #2 - mov \tmp2, #0xf - mov \tmp2, \tmp2, lsl \tmp1 - mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC - str \tmp2, [\tmp1] @ invalidate SCU tags for CPU +#ifdef CONFIG_HAVE_ARM_SCU + check_cpu_part_num 0xc09, \tmp1, \tmp2 + mrceq p15, 0, \tmp1, c0, c0, 5 + andeq \tmp1, \tmp1, #0xF + moveq \tmp1, \tmp1, lsl #2 + moveq \tmp2, #0xf + moveq \tmp2, \tmp2, lsl \tmp1 + ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC) + streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU dsb +#endif .endm /* Macro to check Tegra revision */