From patchwork Mon Jun 3 08:10:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 2651131 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 5E6173FC23 for ; Mon, 3 Jun 2013 08:11:28 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjPrS-0000v4-A4; Mon, 03 Jun 2013 08:11:26 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjPrP-0008So-KQ; Mon, 03 Jun 2013 08:11:23 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjPrH-0008SH-U7 for linux-arm-kernel@lists.infradead.org; Mon, 03 Jun 2013 08:11:16 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 03 Jun 2013 01:10:42 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 03 Jun 2013 01:10:14 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 03 Jun 2013 01:10:14 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.298.1; Mon, 3 Jun 2013 01:10:43 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH] ARM: tegra: remove the ifdef of ARCH SoC in the tegra_resume Date: Mon, 3 Jun 2013 16:10:04 +0800 Message-ID: <1370247004-31846-1-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.3 X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130603_041116_077848_25742F99 X-CRM114-Status: UNSURE ( 9.22 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.4 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Removing the ifdef of ARCH_TEGRA_SoC in the tegra_resume function. Because we always build with all Tegra SoCs support and had a runtime chip detection code there. And we expect most of the chips would need the code in the future. We also fix a typo of a macro name that cause a build error. Reported-by: Arnd Bergmann Signed-off-by: Joseph Lo --- arch/arm/mach-tegra/reset-handler.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index d2042ac..39dc9e7 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -54,12 +54,11 @@ ENTRY(tegra_resume) bne cpu_resume @ no no_cpu0_chk: -#ifndef CONFIG_ARCH_TEGRA_2x_SOC /* Are we on Tegra20? */ cmp r6, #TEGRA20 beq 1f @ Yes /* Clear the flow controller flags for this CPU. */ - cpu_to_csr_req r1, r0 + cpu_to_csr_reg r1, r0 mov32 r2, TEGRA_FLOW_CTRL_BASE ldr r1, [r2, r1] /* Clear event & intr flag */ @@ -70,7 +69,6 @@ no_cpu0_chk: bic r1, r1, r0 str r1, [r2] 1: -#endif check_cpu_part_num 0xc09, r8, r9 bne not_ca9