From patchwork Tue Jun 4 15:05:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2660111 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 780EE40077 for ; Tue, 4 Jun 2013 15:08:09 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ujsoq-0001MR-VJ; Tue, 04 Jun 2013 15:06:41 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjsoY-0007we-DN; Tue, 04 Jun 2013 15:06:22 +0000 Received: from mail-pb0-x22a.google.com ([2607:f8b0:400e:c01::22a]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjsoV-0007tx-Kf for linux-arm-kernel@lists.infradead.org; Tue, 04 Jun 2013 15:06:20 +0000 Received: by mail-pb0-f42.google.com with SMTP id uo1so374707pbc.1 for ; Tue, 04 Jun 2013 08:05:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=o0V/Fwn65NY1t98Xzfm2rMpkHj+5HRtdHo8yjSUIQdU=; b=hz33VhRTlQjWOgsAPYix5bcF4jWkgOWpPbz3uY9vVg68sPmQ1xsLoaVyfOMuINwf2X U7ASECgi+8vT/C53UBj0d+2F3L4Js78I4v0tpHcPuVMX7x/wtswL11TuFQ/+/euM59Jl hjDtB8JHzDuLRSTVQ+CZR8b8WJTOoesnnD6N+UrJ0gUjR0jw9tttEw/Nxb5PupT65AHg 8i2rlrzjDQLHfUY7taUJn4rsKEWn8aztABZFVTT3J0vRwFWo7tgNC02REvJ1JgEbV6ye U1+CyoXtvbFXLGDXThWRdv0yM6Y/QvNAisDSWcBDEI6F+ePaOkUICHrT9Awlot36Osjr 92PQ== X-Received: by 10.66.19.234 with SMTP id i10mr29523257pae.152.1370358353721; Tue, 04 Jun 2013 08:05:53 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id ig4sm35557031pbc.18.2013.06.04.08.05.40 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 04 Jun 2013 08:05:53 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, pawel.moll@arm.com, swarren@nvidia.com, john.stultz@linaro.org, tglx@linutronix.de, mturquette@linaro.org Subject: [PATCH v2 2/6] clk: mux: add CLK_MUX_HIWORD_MASK Date: Tue, 4 Jun 2013 23:05:13 +0800 Message-Id: <1370358317-12768-3-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370358317-12768-1-git-send-email-haojian.zhuang@linaro.org> References: <1370358317-12768-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQliztYIc07el4eebuV5XzWQdH4KSC1Exa1UR3EF/g5+nqXl/chRWSP2rwHm93r6EFcqkbAt X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130604_110619_780915_B031FA03 X-CRM114-Status: GOOD ( 13.29 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org There's a HIWORD mask field in Hisilicon Hi3620 clock mux register. This field must be set while update the clk mux register. In order to reuse the clk-mux driver, append the CLK_MUX_HIWORD_MASK field into mux->flags. Signed-off-by: Haojian Zhuang --- drivers/clk/clk-mux.c | 8 ++++++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 25b1734..887f462 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -70,6 +70,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct clk_mux *mux = to_clk_mux(hw); u32 val; + u8 width = 0; unsigned long flags = 0; if (mux->table) @@ -89,6 +90,13 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) val = readl(mux->reg); val &= ~(mux->mask << mux->shift); val |= index << mux->shift; + if (mux->flags & CLK_MUX_HIWORD_MASK) { + width = fls(mux->mask) - ffs(mux->mask) + 1; + if (width + mux->shift > 16) + pr_warn("mux value exceeds LOWORD field\n"); + else + val |= mux->mask << (mux->shift + 16); + } writel(val, mux->reg); if (mux->lock) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 1186098..6ba32bc 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -299,6 +299,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, * Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) + * CLK_MUX_HIWORD_MASK - register contains high 16-bit as mask field */ struct clk_mux { struct clk_hw hw; @@ -312,6 +313,7 @@ struct clk_mux { #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) +#define CLK_MUX_HIWORD_MASK BIT(2) extern const struct clk_ops clk_mux_ops;