From patchwork Tue Jun 4 15:05:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2660121 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id ED877DF2A1 for ; Tue, 4 Jun 2013 15:08:37 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ujsp4-0001OS-R8; Tue, 04 Jun 2013 15:06:56 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ujsof-0007x7-5s; Tue, 04 Jun 2013 15:06:29 +0000 Received: from mail-pd0-f182.google.com ([209.85.192.182]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjsoW-0007uU-Ql for linux-arm-kernel@lists.infradead.org; Tue, 04 Jun 2013 15:06:21 +0000 Received: by mail-pd0-f182.google.com with SMTP id g10so371724pdj.41 for ; Tue, 04 Jun 2013 08:05:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=hTHWrSyMJFmVH+eYLIwxJRS68HtNud49A3GB9h7mXq0=; b=g33JvWHdHoWaBMYenq+ksNHxkieJASZHnmpD6UMw8bx4GUS+9RulCmU0+cS+BFLFpU XnzvWkkcpRfYC53o/j68RHi4m0zElkcipbX7enSHHrrkbsbRns0LoEJ3AqJSAuRuP3JB pL0d/kDBl9orVrCHJk/k/BDZVhvPIw3WSqLMnzNfED4f+KiL+7YWES8rmgnU+1U163bF 6gTlL16wPDDJmnY2HPbiY6Lus5vKLxhYsD3R8DPvnfkfQS1TPz6H2CKKJ7e/XgqJhqfO NmHmyRhrCIhhqcToLGh3rXxtLpw3hzonGyG9EEJsbtkDEuMLnJg8aEaEey5Gtr3W+e8W 2zpg== X-Received: by 10.68.71.129 with SMTP id v1mr29374459pbu.136.1370358359429; Tue, 04 Jun 2013 08:05:59 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id ig4sm35557031pbc.18.2013.06.04.08.05.54 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 04 Jun 2013 08:05:58 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, pawel.moll@arm.com, swarren@nvidia.com, john.stultz@linaro.org, tglx@linutronix.de, mturquette@linaro.org Subject: [PATCH v2 3/6] clk: divider: add CLK_DIVIDER_HIWORD_MASK flag Date: Tue, 4 Jun 2013 23:05:14 +0800 Message-Id: <1370358317-12768-4-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370358317-12768-1-git-send-email-haojian.zhuang@linaro.org> References: <1370358317-12768-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQkTsvM526vLdWLvpgjblJ+pYXOmycY0lb06PE+0Mh5UcLNe4ak17EoLylz/QEMSUHC5g/Ge X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130604_110620_939864_7B3D4B90 X-CRM114-Status: GOOD ( 11.12 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.192.182 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In Hisilicon Hi3620 clock divider register, 16-bit HIWORD is mask field. Support the HIWORD mask to reuse clock divider driver. Signed-off-by: Haojian Zhuang --- drivers/clk/clk-divider.c | 6 ++++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 6d96741..4c344b4 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -220,6 +220,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, val = readl(divider->reg); val &= ~(div_mask(divider) << divider->shift); val |= value << divider->shift; + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + if (divider->width + divider->shift > 16) + pr_warn("divider value exceeds LOWORD field\n"); + else + val |= div_mask(divider) << (divider->shift + 16); + } writel(val, divider->reg); if (divider->lock) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 6ba32bc..dbb9bd9 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -257,6 +257,7 @@ struct clk_div_table { * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). + * CLK_DIVIDER_HIWORD_MASK - register contains high 16-bit as mask field */ struct clk_divider { struct clk_hw hw; @@ -271,6 +272,7 @@ struct clk_divider { #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) extern const struct clk_ops clk_divider_ops; struct clk *clk_register_divider(struct device *dev, const char *name,