From patchwork Wed Jun 5 21:18:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2674831 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 6370B3FD4F for ; Wed, 5 Jun 2013 21:25:19 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UkL9A-0005dK-O5; Wed, 05 Jun 2013 21:21:36 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UkL7z-0007RF-FV; Wed, 05 Jun 2013 21:20:19 +0000 Received: from mail-bk0-x229.google.com ([2a00:1450:4008:c01::229]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UkL6r-0007Fv-Bs for linux-arm-kernel@lists.infradead.org; Wed, 05 Jun 2013 21:19:17 +0000 Received: by mail-bk0-f41.google.com with SMTP id jc3so1190632bkc.0 for ; Wed, 05 Jun 2013 14:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=2wLZwgroLLhRbln9WtYSN9omn2jX5K3vqGtotkCW/xQ=; b=p051lf2ME8e16dVxmLw9BpXJnLqDdaRNOVn+KrK2WDv7+2UTcu1NGurqLRLyjZloBl N2skejvXY3sA4LRqaBbRvh0CLx2HplbSK5NxbIL8RtgC7ZA7Rd9i0pLZT1TMF8th2iM5 oKEd3WJt/Y1IGA4yGjNC/2JDGWI+kQMUtOMrEyGB8yD6rqXLlpiploqoGU8f8Jz9TJVg jsxbeJz61Lgh47vtwON0OsQbEd+LrW18SeDHCctis2Fe3mzNCO50nT7EopxAmKPI2QkL KNjXFxq3+FhKi59uKUvA/EXCc8yx+D35r6o+TjSVFoUryXWkuwkLNegj5K8eMoRxbh4M j5PA== X-Received: by 10.204.224.15 with SMTP id im15mr10322209bkb.120.1370467131816; Wed, 05 Jun 2013 14:18:51 -0700 (PDT) Received: from flatron.tomeq (87-207-52-162.dynamic.chello.pl. [87.207.52.162]) by mx.google.com with ESMTPSA id iy11sm26540425bkb.11.2013.06.05.14.18.49 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Jun 2013 14:18:51 -0700 (PDT) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/15] pwm: Add new pwm-samsung driver Date: Wed, 5 Jun 2013 23:18:13 +0200 Message-Id: <1370467100-10820-9-git-send-email-tomasz.figa@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1370467100-10820-1-git-send-email-tomasz.figa@gmail.com> References: <1370467100-10820-1-git-send-email-tomasz.figa@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130605_171910_004256_6C807411 X-CRM114-Status: GOOD ( 27.76 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (tomasz.figa[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: linux-pwm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, =?UTF-8?q?Heiko=20St=C3=BCbner?= , Arnd Bergmann , Mark Brown , Tomasz Figa , thierry.reding@gmail.com, Thomas Abraham , Olof Johansson , Kukjin Kim , Sylwester Nawrocki X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch introduces new Samsung PWM driver, which uses Samsung PWM/timer master driver to control shared parts of the hardware. Signed-off-by: Tomasz Figa --- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-samsung.c | 528 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 529 insertions(+) create mode 100644 drivers/pwm/pwm-samsung.c diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 229a599..833c3ac 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung-legacy.o +obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c new file mode 100644 index 0000000..61bed3d --- /dev/null +++ b/drivers/pwm/pwm-samsung.c @@ -0,0 +1,528 @@ +/* drivers/pwm/pwm-samsung.c + * + * Copyright (c) 2007 Ben Dooks + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks , + * Copyright (c) 2013 Tomasz Figa + * + * PWM driver for Samsung SoCs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define REG_TCFG0 0x00 +#define REG_TCFG1 0x04 +#define REG_TCON 0x08 + +#define REG_TCNTB(tmr) (0x0c + ((tmr) * 0xc)) +#define REG_TCMPB(tmr) (0x10 + ((tmr) * 0xc)) + +#define TCFG0_PRESCALER_MASK 0xff +#define TCFG0_PRESCALER1_SHIFT 8 + +#define TCFG1_MUX_MASK 0xf +#define TCFG1_SHIFT(x) ((x) * 4) + +#define TCON_START(chan) (1 << (4 * (chan) + 0)) +#define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1)) +#define TCON_INVERT(chan) (1 << (4 * (chan) + 2)) +#define TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3)) + +struct samsung_pwm_channel { + unsigned long period_ns; + unsigned long duty_ns; + unsigned long tin_ns; +}; + +struct samsung_pwm_chip { + struct pwm_chip chip; + struct samsung_pwm_variant variant; + struct samsung_pwm_channel channels[SAMSUNG_PWM_NUM]; + + void __iomem *base; + struct clk *base_clk; + struct clk *tclk0; + struct clk *tclk1; +}; +#define to_samsung_pwm_chip(chip) \ + container_of(chip, struct samsung_pwm_chip, chip) + +#ifndef CONFIG_CLKSRC_SAMSUNG_PWM +static DEFINE_SPINLOCK(samsung_pwm_lock); +#endif + +static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm, + unsigned int channel, u8 divisor) +{ + u8 shift = TCFG1_SHIFT(channel); + unsigned long flags; + u32 reg; + u8 bits; + + bits = (fls(divisor) - 1) - pwm->variant.div_base; + + spin_lock_irqsave(&samsung_pwm_lock, flags); + + reg = readl(pwm->base + REG_TCFG1); + reg &= ~(TCFG1_MUX_MASK << shift); + reg |= bits << shift; + writel(reg, pwm->base + REG_TCFG1); + + spin_unlock_irqrestore(&samsung_pwm_lock, flags); +} + +static inline int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, + unsigned int chan) +{ + struct samsung_pwm_variant *variant = &chip->variant; + u32 reg; + + reg = readl(chip->base + REG_TCFG1); + reg >>= TCFG1_SHIFT(chan); + reg &= TCFG1_MUX_MASK; + + return ((1 << reg) & variant->tclk_mask) == 0; +} + +static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip, + unsigned int chan) +{ + unsigned long rate; + u32 reg; + + rate = clk_get_rate(chip->base_clk); + + reg = readl(chip->base + REG_TCFG0); + if (chan >= 2) + reg >>= TCFG0_PRESCALER1_SHIFT; + reg &= TCFG0_PRESCALER_MASK; + + return rate / (reg + 1); +} + +static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip, + unsigned int chan, unsigned long freq) +{ + struct samsung_pwm_variant *variant = &chip->variant; + unsigned long rate; + unsigned int div; + struct clk *clk; + + if (!pwm_samsung_is_tdiv(chip, chan)) { + clk = (chan < 2) ? chip->tclk0 : chip->tclk1; + if (!IS_ERR(clk)) { + rate = clk_get_rate(clk); + if (rate) + return rate; + } + + dev_warn(chip->chip.dev, + "tclk of PWM %d is inoperational, using tdiv\n", chan); + } + + rate = pwm_samsung_get_tin_rate(chip, chan); + dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate); + + /* + * Compare minimum PWM frequency that can be achieved with possible + * divider settings and choose the lowest divisor that can generate + * frequencies lower than requested. + */ + for (div = variant->div_base; div < 4; ++div) + if ((rate >> (variant->bits + div)) < freq) + break; + + pwm_samsung_set_divisor(chip, chan, 1 << div); + + return rate >> div; +} + +static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + + if (our_chip->variant.output_mask & (1 << pwm->hwpwm)) + return 0; + + dev_warn(our_chip->chip.dev, + "tried to request PWM channel %d without output\n", + pwm->hwpwm); + + return -EINVAL; +} + +static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + unsigned int channel = pwm->hwpwm; + unsigned long tcon; + unsigned long flags; + + if (channel > 0) + ++channel; + + spin_lock_irqsave(&samsung_pwm_lock, flags); + + tcon = __raw_readl(our_chip->base + REG_TCON); + + tcon &= ~TCON_MANUALUPDATE(channel); + tcon |= TCON_START(channel) | TCON_AUTORELOAD(channel); + + __raw_writel(tcon, our_chip->base + REG_TCON); + + spin_unlock_irqrestore(&samsung_pwm_lock, flags); + + return 0; +} + +static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + unsigned int channel = pwm->hwpwm; + unsigned long tcon; + unsigned long flags; + + if (channel > 0) + ++channel; + + spin_lock_irqsave(&samsung_pwm_lock, flags); + + tcon = __raw_readl(our_chip->base + REG_TCON); + tcon &= ~TCON_AUTORELOAD(channel); + __raw_writel(tcon, our_chip->base + REG_TCON); + + spin_unlock_irqrestore(&samsung_pwm_lock, flags); +} + +static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + struct samsung_pwm_channel *chan = &our_chip->channels[pwm->hwpwm]; + unsigned long tin_ns = chan->tin_ns; + unsigned int tcon_chan = pwm->hwpwm; + unsigned long tin_rate; + unsigned long period; + unsigned long flags; + unsigned long tcnt; + long tcmp; + u32 tcon; + + /* We currently avoid using 64bit arithmetic by using the + * fact that anything faster than 1Hz is easily representable + * by 32bits. */ + if (period_ns > NSEC_PER_SEC || duty_ns > NSEC_PER_SEC) + return -ERANGE; + + if (period_ns == chan->period_ns && duty_ns == chan->duty_ns) + return 0; + + /* The TCMP and TCNT can be read without a lock, they're not + * shared between the timers. */ + tcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm)); + tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); + + period = NSEC_PER_SEC / period_ns; + + dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%lu)\n", + duty_ns, period_ns, period); + + /* Check to see if we are changing the clock rate of the PWM */ + if (chan->period_ns != period_ns) { + tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period); + + chan->period_ns = period_ns; + + dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate); + + tin_ns = NSEC_PER_SEC / tin_rate; + tcnt = period_ns / tin_ns; + + chan->tin_ns = tin_ns; + } + + /* Note, counters count down */ + tcmp = duty_ns / tin_ns; + tcmp = tcnt - tcmp; + + /* the pwm hw only checks the compare register after a decrement, + so the pin never toggles if tcmp = tcnt */ + if (tcmp == tcnt) + tcmp--; + + dev_dbg(our_chip->chip.dev, "tin_ns=%lu, tcmp=%ld/%lu\n", + tin_ns, tcmp, tcnt); + + if (tcmp < 0) + tcmp = 0; + + /* Update the PWM register block. */ + if (tcon_chan > 0) + ++tcon_chan; + + spin_lock_irqsave(&samsung_pwm_lock, flags); + + tcon = __raw_readl(our_chip->base + REG_TCON); + + tcnt--; + + tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan)); + tcon |= TCON_MANUALUPDATE(tcon_chan); + + __raw_writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm)); + __raw_writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm)); + __raw_writel(tcon, our_chip->base + REG_TCON); + + spin_unlock_irqrestore(&samsung_pwm_lock, flags); + + return 0; +} + +static int pwm_samsung_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, enum pwm_polarity polarity) +{ + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + unsigned int channel = pwm->hwpwm; + unsigned long flags; + u32 tcon; + + if (channel > 0) + ++channel; + + spin_lock_irqsave(&samsung_pwm_lock, flags); + + tcon = __raw_readl(our_chip->base + REG_TCON); + + /* Invert in hardware means normal polarity of PWM core */ + if (polarity == PWM_POLARITY_NORMAL) + tcon |= TCON_INVERT(channel); + else + tcon &= ~TCON_INVERT(channel); + + __raw_writel(tcon, our_chip->base + REG_TCON); + + spin_unlock_irqrestore(&samsung_pwm_lock, flags); + + return 0; +} + +static struct pwm_ops pwm_samsung_ops = { + .request = pwm_samsung_request, + .enable = pwm_samsung_enable, + .disable = pwm_samsung_disable, + .config = pwm_samsung_config, + .set_polarity = pwm_samsung_set_polarity, + .owner = THIS_MODULE, +}; + +#ifdef CONFIG_OF +static const struct samsung_pwm_variant s3c24xx_variant = { + .bits = 16, + .div_base = 1, + .has_tint_cstat = false, + .tclk_mask = (1 << 4), +}; + +static const struct samsung_pwm_variant s3c64xx_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5), +}; + +static const struct samsung_pwm_variant s5p64x0_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = 0, +}; + +static const struct samsung_pwm_variant s5p_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = (1 << 5), +}; + +static const struct of_device_id samsung_pwm_matches[] = { + { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant }, + { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant }, + { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant }, + { .compatible = "samsung,s5pc100-pwm", .data = &s5p_variant }, + { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant }, + {}, +}; +#endif + +static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) +{ + struct device_node *np = chip->chip.dev->of_node; + const struct of_device_id *match; + struct property *prop; + const __be32 *cur; + u32 val; + + match = of_match_node(samsung_pwm_matches, np); + if (!match) + return -ENODEV; + + memcpy(&chip->variant, match->data, sizeof(chip->variant)); + + of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { + if (val >= SAMSUNG_PWM_NUM) { + pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n", + __func__); + continue; + } + chip->variant.output_mask |= 1 << val; + } + + return 0; +} + +static int pwm_samsung_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct samsung_pwm_chip *chip; + struct resource *res; + int ret; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (chip == NULL) { + dev_err(dev, "failed to allocate driver data\n"); + return -ENOMEM; + } + + chip->chip.dev = &pdev->dev; + chip->chip.ops = &pwm_samsung_ops; + chip->chip.base = -1; + chip->chip.npwm = SAMSUNG_PWM_NUM; + + if (pdev->dev.of_node) { + ret = pwm_samsung_parse_dt(chip); + if (ret) + return ret; + + chip->chip.of_xlate = of_pwm_xlate_with_flags; + chip->chip.of_pwm_n_cells = 3; + } else { + if (!pdev->dev.platform_data) { + dev_err(&pdev->dev, "no platform data specified\n"); + return -EINVAL; + } + + memcpy(&chip->variant, pdev->dev.platform_data, + sizeof(chip->variant)); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get mem resource\n"); + return -ENOMEM; + } + + chip->base = devm_request_and_ioremap(&pdev->dev, res); + if (!chip->base) { + dev_err(&pdev->dev, "failed to request and map registers\n"); + return -ENOMEM; + } + + chip->base_clk = devm_clk_get(&pdev->dev, "timers"); + if (IS_ERR(chip->base_clk)) { + dev_err(dev, "failed to get timer base clk\n"); + return PTR_ERR(chip->base_clk); + } + clk_prepare_enable(chip->base_clk); + + chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0"); + chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1"); + + ret = pwmchip_add(&chip->chip); + if (ret < 0) { + dev_err(dev, "failed to register pwm\n"); + goto err_clk_disable; + } + + dev_info(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n", + clk_get_rate(chip->base_clk), + !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0, + !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0); + + platform_set_drvdata(pdev, chip); + + return 0; + +err_clk_disable: + clk_disable_unprepare(chip->base_clk); + + return ret; +} + +static int pwm_samsung_remove(struct platform_device *pdev) +{ + struct samsung_pwm_chip *chip = platform_get_drvdata(pdev); + int err; + + err = pwmchip_remove(&chip->chip); + if (err < 0) + return err; + + clk_disable_unprepare(chip->base_clk); + + return 0; +} + +#ifdef CONFIG_PM +static int pwm_samsung_suspend(struct device *dev) +{ + struct samsung_pwm_chip *chip = dev_get_drvdata(dev); + int i; + + /* No one preserve these values during suspend so reset them + * Otherwise driver leaves PWM unconfigured if same values + * passed to pwm_config + */ + for (i = 0; i < SAMSUNG_PWM_NUM; ++i) { + chip->channels[i].period_ns = 0; + chip->channels[i].duty_ns = 0; + } + + return 0; +} +#endif + +static struct dev_pm_ops pwm_samsung_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pwm_samsung_suspend, NULL) +}; + +static struct platform_driver pwm_samsung_driver = { + .driver = { + .name = "samsung-pwm", + .owner = THIS_MODULE, + .pm = &pwm_samsung_pm_ops, + .of_match_table = of_match_ptr(samsung_pwm_matches), + }, + .probe = pwm_samsung_probe, + .remove = pwm_samsung_remove, +}; +module_platform_driver(pwm_samsung_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tomasz Figa "); +MODULE_ALIAS("platform:samsung-pwm");