From patchwork Thu Jun 6 07:28:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 2677741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 8CAE6DF23A for ; Thu, 6 Jun 2013 07:33:17 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UkUes-0001m4-TB; Thu, 06 Jun 2013 07:30:57 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UkUdz-0007xK-3X; Thu, 06 Jun 2013 07:29:59 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UkUd5-0007k4-Dz for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2013 07:29:06 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Thu, 06 Jun 2013 00:35:22 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 06 Jun 2013 00:27:46 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 06 Jun 2013 00:27:46 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.298.1; Thu, 6 Jun 2013 00:28:27 -0700 From: Alexandre Courbot To: Stephen Warren , Joseph Lo , Karan Jhavar , Varun Wadekar , Chris Johnson , Matthew Longnecker Subject: [PATCH] ARM: tegra: add basic SecureOS support Date: Thu, 6 Jun 2013 16:28:07 +0900 Message-ID: <1370503687-17767-1-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.8.3 X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130606_032903_739545_14A18081 X-CRM114-Status: GOOD ( 23.82 ) X-Spam-Score: -7.4 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: gnurou@gmail.com, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Alexandre Courbot , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Boot loaders on some Tegra devices can be unlocked but do not let the system operate without SecureOS. SecureOS prevents access to some registers and requires the operating system to perform certain operations through Secure Monitor Calls instead of directly accessing the hardware. This patch introduces basic SecureOS support for Tegra. SecureOS support can be enabled by adding a "nvidia,secure-os" property to the "chosen" node of the device tree. Currently, only the bringup of secondary CPUs is performed by SMCs, but more operations will be added later. Signed-off-by: Alexandre Courbot --- Documentation/devicetree/bindings/arm/tegra.txt | 8 +++ arch/arm/configs/tegra_defconfig | 1 + arch/arm/mach-tegra/Kconfig | 11 ++++ arch/arm/mach-tegra/Makefile | 2 + arch/arm/mach-tegra/common.c | 2 + arch/arm/mach-tegra/reset.c | 30 +++++++---- arch/arm/mach-tegra/secureos.c | 70 +++++++++++++++++++++++++ arch/arm/mach-tegra/secureos.h | 31 +++++++++++ 8 files changed, 145 insertions(+), 10 deletions(-) create mode 100644 arch/arm/mach-tegra/secureos.c create mode 100644 arch/arm/mach-tegra/secureos.h diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index ed9c853..b543091 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -32,3 +32,11 @@ board-specific compatible values: nvidia,whistler toradex,colibri_t20-512 toradex,iris + +Global properties +------------------------------------------- + +The following properties can be specified into the "chosen" root +node: + + nvidia,secure-os: enable SecureOS. diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index f7ba3161..f6ed0f5 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -28,6 +28,7 @@ CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_ARCH_TEGRA_114_SOC=y CONFIG_TEGRA_PCI=y CONFIG_TEGRA_EMC_SCALING_ENABLE=y +CONFIG_TEGRA_SECUREOS=y CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_AEABI=y diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 84d72fc..acb5d0a 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -87,4 +87,15 @@ config TEGRA_AHB config TEGRA_EMC_SCALING_ENABLE bool "Enable scaling the memory frequency" +config TEGRA_SECUREOS + bool "Enable SecureOS support" + help + Support for Tegra devices which bootloader sets up a + SecureOS environment. This will use Secure Monitor Calls + instead of directly accessing the hardware for some protected + operations. + + SecureOS support is enabled by declaring a "nvidia,secure-os" + property into the "chosen" node of the device tree. + endmenu diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index d011f0a..3adafe6 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -37,3 +37,5 @@ endif obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o + +obj-$(CONFIG_TEGRA_SECUREOS) += secureos.o diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 9f852c6..b7eea02 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -37,6 +37,7 @@ #include "sleep.h" #include "pm.h" #include "reset.h" +#include "secureos.h" /* * Storage for debug-macro.S's state. @@ -97,6 +98,7 @@ static void __init tegra_init_cache(void) void __init tegra_init_early(void) { + tegra_init_secureos(); tegra_cpu_reset_handler_init(); tegra_apb_io_init(); tegra_init_fuse(); diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 1ac434e..4b9ebf9 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -21,38 +21,32 @@ #include #include +#include #include "iomap.h" #include "irammap.h" #include "reset.h" #include "sleep.h" #include "fuse.h" +#include "secureos.h" #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \ TEGRA_IRAM_RESET_HANDLER_OFFSET) static bool is_enabled; -static void __init tegra_cpu_reset_handler_enable(void) +static void __init tegra_cpu_reset_handler_set(const u32 reset_address) { - void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); void __iomem *evp_cpu_reset = IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); u32 reg; - BUG_ON(is_enabled); - BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); - - memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, - tegra_cpu_reset_handler_size); - /* * NOTE: This must be the one and only write to the EVP CPU reset * vector in the entire system. */ - writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset, - evp_cpu_reset); + writel(reset_address, evp_cpu_reset); wmb(); reg = readl(evp_cpu_reset); @@ -66,6 +60,22 @@ static void __init tegra_cpu_reset_handler_enable(void) writel(reg, sb_ctrl); wmb(); } +} + +static void __init tegra_cpu_reset_handler_enable(void) +{ + void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); + const u32 reset_address = TEGRA_IRAM_RESET_BASE + + tegra_cpu_reset_handler_offset; + + BUG_ON(is_enabled); + BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); + + memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, + tegra_cpu_reset_handler_size); + + if (call_firmware_op(set_cpu_boot_addr, 0, reset_address) == -ENOSYS) + tegra_cpu_reset_handler_set(reset_address); is_enabled = true; } diff --git a/arch/arm/mach-tegra/secureos.c b/arch/arm/mach-tegra/secureos.c new file mode 100644 index 0000000..44c3514 --- /dev/null +++ b/arch/arm/mach-tegra/secureos.c @@ -0,0 +1,70 @@ +/* + * SecureOS support for Tegra CPUs + * + * Copyright (c) 2013, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include + +static int __attribute__((used)) __tegra_smc_stack[10]; + +/* + * With EABI, subtype and arg already end up in r0, r1 and r2 as they are + * function arguments, but we prefer to play safe here and explicitly move + * these values into the expected registers anyway. mov instructions without + * any side-effect are turned into nops by the assembler, which limits + * overhead. + */ +static void tegra_generic_smc(u32 type, u32 subtype, u32 arg) +{ + asm volatile( + ".arch_extension sec\n\t" + "ldr r3, =__tegra_smc_stack\n\t" + "stmia r3, {r4-r12, lr}\n\t" + "mov r0, %[type]\n\t" + "mov r1, %[subtype]\n\t" + "mov r2, %[arg]\n\t" + "mov r3, #0\n\t" + "mov r4, #0\n\t" + "dsb\n\t" + "smc #0\n\t" + "ldr r3, =__tegra_smc_stack\n\t" + "ldmia r3, {r4-r12, lr}" + : + : [type] "r" (type), + [subtype] "r" (subtype), + [arg] "r" (arg) + : "r0", "r1", "r2", "r3", "r4", "memory"); +} + +static int tegra_set_cpu_boot_addr(int cpu, unsigned long boot_addr) +{ + tegra_generic_smc(0xfffff200, boot_addr, 0); + + return 0; +} + +static const struct firmware_ops tegra_firmware_ops = { + .set_cpu_boot_addr = tegra_set_cpu_boot_addr, +}; + +void __init tegra_init_secureos(void) +{ + struct device_node *node = of_find_node_by_path("/chosen"); + + if (node && of_property_read_bool(node, "nvidia,secure-os")) + register_firmware_ops(&tegra_firmware_ops); +} diff --git a/arch/arm/mach-tegra/secureos.h b/arch/arm/mach-tegra/secureos.h new file mode 100644 index 0000000..5388cc5 --- /dev/null +++ b/arch/arm/mach-tegra/secureos.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TEGRA_SECUREOS_H +#define __TEGRA_SECUREOS_H + +#ifdef CONFIG_TEGRA_SECUREOS + +#include + +void tegra_init_secureos(void); + +#else + +static inline void tegra_init_secureos(void) +{ +} + +#endif + +#endif