| Message ID | 1370516488-25860-1-git-send-email-chander.kashyap@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Exynos5420 is new SoC in Samsung's Exynos5 SoC series.
Patches 1 and 2 are generic enhancement patches applicable for all
Exynos based SoCs.
Patches 3 and 4 factor out the common DT nodes for Exynos5 based SoCs.
Remaining patches provide support for Exynos5420 SoC and SMDK5420 board.
Chander Kashyap (13):
ARM: Exynos: initialize l2x0 cache controller only for cortex-a9
based SoCs
ARM: Exynos: fix secondary cpu power control register address
calculation
ARM: dts: fork out common Exynos5 nodes
ARM: dts: list the CPU nodes for Exynos5250
ARM: Exynos: Add support for Exynos5420 SoC
serial: samsung: add support for Exynos5420
ARM: Exynos: use four additional chipid bits to identify Exynos
family
irqchip: exynos-combiner: set irq base as 256 for Exynos5420
clk: exynos5420: register clocks using common clock framework
ARM: dts: Add initial device tree support for Exynos5420
clocksource: exynos_mct: extend local timer support for four cores
ARM: Exynos: add secondary CPU boot base location for Exynos5420
ARM: Exynos: extend soft-reset support for Exynos5420
.../devicetree/bindings/clock/exynos5420-clock.txt | 201 ++++++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5.dtsi | 121 ++++
arch/arm/boot/dts/exynos5250.dtsi | 84 +--
arch/arm/boot/dts/exynos5420-smdk5420.dts | 40 +
arch/arm/boot/dts/exynos5420.dtsi | 101 +++
arch/arm/mach-exynos/Kconfig | 10 +
arch/arm/mach-exynos/common.c | 13 +-
arch/arm/mach-exynos/include/mach/regs-pmu.h | 6 +
arch/arm/mach-exynos/include/mach/uncompress.h | 7 +-
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/mach-exynos/platsmp.c | 22 +-
arch/arm/plat-samsung/include/plat/cpu.h | 8 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5420.c | 762 ++++++++++++++++++++
drivers/clocksource/exynos_mct.c | 33 +-
drivers/irqchip/exynos-combiner.c | 5 +-
drivers/tty/serial/samsung.c | 2 +-
18 files changed, 1328 insertions(+), 90 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5420-clock.txt
create mode 100644 arch/arm/boot/dts/exynos5.dtsi
create mode 100644 arch/arm/boot/dts/exynos5420-smdk5420.dts
create mode 100644 arch/arm/boot/dts/exynos5420.dtsi
create mode 100644 drivers/clk/samsung/clk-exynos5420.c
Hi Chander, On Thursday 06 of June 2013 16:31:15 Chander Kashyap wrote: > Only cortex-a9 based Exynos SoCs have l2x0 cache controller. Hence > instead of checking for every SoC with soc_is_xxx, just check for cpu > part number and initialize the cache controller for cortex-a9 based > SoCs. > > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> > --- > arch/arm/mach-exynos/common.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-exynos/common.c > b/arch/arm/mach-exynos/common.c index 8ce2db4..bad000e 100644 > --- a/arch/arm/mach-exynos/common.c > +++ b/arch/arm/mach-exynos/common.c > @@ -35,6 +35,7 @@ > #include <asm/mach/map.h> > #include <asm/mach/irq.h> > #include <asm/cacheflush.h> > +#include <asm/cputype.h> > > #include <mach/regs-irq.h> > #include <mach/regs-pmu.h> > @@ -520,7 +521,7 @@ static int __init exynos4_l2x0_cache_init(void) I wonder if it shouldn't be done the other way around, i.e. this function being called only when running on SoCs for which it's appropriate, instead of checking for supported SoC in this function. Keep in mind that we are going towards multiplatform support, so you would end up running this code on any non-Exynos SoC with Cortex A9 as well. IMHO we should drop most (if not all) of the initcalls around mach- exynos/. CCing people that might have some opinion on this topic as well. Best regards, Tomasz > { > int ret; > > - if (soc_is_exynos5250() || soc_is_exynos5440()) > + if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9) > return 0; > > ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
On Sat, Jun 08, 2013 at 12:57:41PM +0200, Tomasz Figa wrote: > Hi Chander, > > On Thursday 06 of June 2013 16:31:15 Chander Kashyap wrote: > > Only cortex-a9 based Exynos SoCs have l2x0 cache controller. Hence > > instead of checking for every SoC with soc_is_xxx, just check for cpu > > part number and initialize the cache controller for cortex-a9 based > > SoCs. > > > > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> > > --- > > arch/arm/mach-exynos/common.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/mach-exynos/common.c > > b/arch/arm/mach-exynos/common.c index 8ce2db4..bad000e 100644 > > --- a/arch/arm/mach-exynos/common.c > > +++ b/arch/arm/mach-exynos/common.c > > @@ -35,6 +35,7 @@ > > #include <asm/mach/map.h> > > #include <asm/mach/irq.h> > > #include <asm/cacheflush.h> > > +#include <asm/cputype.h> > > > > #include <mach/regs-irq.h> > > #include <mach/regs-pmu.h> > > @@ -520,7 +521,7 @@ static int __init exynos4_l2x0_cache_init(void) > > I wonder if it shouldn't be done the other way around, i.e. this function > being called only when running on SoCs for which it's appropriate, instead > of checking for supported SoC in this function. > > Keep in mind that we are going towards multiplatform support, so you would > end up running this code on any non-Exynos SoC with Cortex A9 as well. > IMHO we should drop most (if not all) of the initcalls around mach- > exynos/. > > CCing people that might have some opinion on this topic as well. Looks like all other platforms instantiate the pl310 device node in the device tree. Since Exynos is going DT-only, there's no need to support non-DT boot any more, and that would be a much cleaner way forward. That also moves the l2 init to be driven by device-tree data, this removing the need for the exynos-specific init alltogether. Code removal FTW! -Olof
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 8ce2db4..bad000e 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -35,6 +35,7 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> #include <asm/cacheflush.h> +#include <asm/cputype.h> #include <mach/regs-irq.h> #include <mach/regs-pmu.h> @@ -520,7 +521,7 @@ static int __init exynos4_l2x0_cache_init(void) { int ret; - if (soc_is_exynos5250() || soc_is_exynos5440()) + if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9) return 0; ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
Only cortex-a9 based Exynos SoCs have l2x0 cache controller. Hence instead of checking for every SoC with soc_is_xxx, just check for cpu part number and initialize the cache controller for cortex-a9 based SoCs. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> --- arch/arm/mach-exynos/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)