From patchwork Thu Jun 6 11:01:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 2679021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 38BCDDF23A for ; Thu, 6 Jun 2013 11:03:14 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UkXyB-00025O-Gp; Thu, 06 Jun 2013 11:03:03 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UkXy8-0004tV-Kg; Thu, 06 Jun 2013 11:03:00 +0000 Received: from mail-pb0-x22e.google.com ([2607:f8b0:400e:c01::22e]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UkXy5-0004sf-H4 for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2013 11:02:58 +0000 Received: by mail-pb0-f46.google.com with SMTP id rq8so748654pbb.33 for ; Thu, 06 Jun 2013 04:02:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=XPFXX/EnoCAZJRDwkdCtNQK9EVsLkM15hLwnywGMfww=; b=kQURdcbh1CnEH67H30Gp+Y9G0CJGy8wEf0GdA1wWv2Fo1fY2XRxalSEfBeWwzaAqZ+ R9rSkDzlC81ov/ypYqr6LftjcptJEqHtUzeFNDaqRI7X//Uwy9xkOwTd2ux8ThpC/XGI k4L8dG9JwVfoqMIgHYZ5zCQQBRuwMHAep5C4ujRPJIU4f902ZUtLqQihE3jg/zUhHpGO FM6e6PSc5yeyyvfJx/8AOq7YjE4Ja+sNTx/F4f/gCQmhR3p0W88opxx64utBafyGf5Pu 2+X6CawE7FrdolVgLZNgqw6+UJ1B2PcHFhtwNtriZXsZTBvpf7MxgtxNScS/UMO5ErzK m3Dg== X-Received: by 10.66.122.130 with SMTP id ls2mr38049134pab.128.1370516554210; Thu, 06 Jun 2013 04:02:34 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id qh4sm77248213pac.8.2013.06.06.04.02.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Jun 2013 04:02:33 -0700 (PDT) From: Chander Kashyap To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 01/13] ARM: Exynos: initialize l2x0 cache controller only for cortex-a9 based SoCs Date: Thu, 6 Jun 2013 16:31:15 +0530 Message-Id: <1370516488-25860-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmfDsYBmllsLtJoAIcCSHshEiZsOunIpS5LKoG9gg0oom961x5Gw3l5kL5LjxHF3ZlI2E17 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130606_070257_645034_64EC3D4D X-CRM114-Status: GOOD ( 10.79 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: kgene.kim@samsung.com, linux-serial@vger.kernel.org, t.figa@samsung.com, Chander Kashyap , linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com, s.nawrocki@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Only cortex-a9 based Exynos SoCs have l2x0 cache controller. Hence instead of checking for every SoC with soc_is_xxx, just check for cpu part number and initialize the cache controller for cortex-a9 based SoCs. Signed-off-by: Chander Kashyap --- arch/arm/mach-exynos/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 8ce2db4..bad000e 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -520,7 +521,7 @@ static int __init exynos4_l2x0_cache_init(void) { int ret; - if (soc_is_exynos5250() || soc_is_exynos5440()) + if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9) return 0; ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);