From patchwork Sat Jun 8 14:47:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2692551 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 8DAB83FC23 for ; Sat, 8 Jun 2013 14:49:00 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UlKRT-000625-62; Sat, 08 Jun 2013 14:48:31 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UlKRL-00078I-R5; Sat, 08 Jun 2013 14:48:23 +0000 Received: from mail-pd0-f170.google.com ([209.85.192.170]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UlKRI-00076Q-Rj for linux-arm-kernel@lists.infradead.org; Sat, 08 Jun 2013 14:48:21 +0000 Received: by mail-pd0-f170.google.com with SMTP id x11so146646pdj.1 for ; Sat, 08 Jun 2013 07:47:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=MUldlKJcoI8JY0SAGvmI6O7ZkZYakPkGHqnk1queg8Q=; b=dlEZ1FHWJM/9LBaSlab5ybMazb2c6a+IRL3TQKd0sDoJ5RsXTP2E5MErQSqI6f40om piXjC/SXWjuul7GW2X/++aAQY6/4lQW8C0UztpyU+hLUb9S0yHv8J+SMsilTXw8D8yA3 k05gcZO+4f7J5u185yrOrOxQ9yg8B1tjPT/cuPuAblUgARyNeFMsfDV8I4SfB4Zp+hed Ls5ssXDidPz/y58j4T8k0eUXwW1X9dwJtxrjfiMUrgqBeDEXPVQZw2RpqN5ef6mvY1M8 nuep79z87xysQDq/Cve2rVOaMy4JvDl8+IFYFoB4PcXlWl7b1Q/q+EOavC+ymPwLPSQW FR3Q== X-Received: by 10.68.176.197 with SMTP id ck5mr3002278pbc.165.1370702877430; Sat, 08 Jun 2013 07:47:57 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id rn7sm3320951pbc.12.2013.06.08.07.47.47 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 08 Jun 2013 07:47:56 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, john.stultz@linaro.org, mturquette@linaro.org, heiko@sntech.de Subject: [PATCH v4 1/7] clk: mux: add CLK_MUX_HIWORD_MASK Date: Sat, 8 Jun 2013 22:47:17 +0800 Message-Id: <1370702843-27172-2-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> References: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQm1Cu6JRaADuBQxuhAfu/OoxbPoq2+4O7qsNU/grfydF5QtSHQEuok886LA/phX+G+KFhFP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130608_104821_024584_9288369A X-CRM114-Status: GOOD ( 15.71 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.192.170 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by: Heiko Stuebner Signed-off-by: Haojian Zhuang --- drivers/clk/clk-mux.c | 17 +++++++++++++++-- include/linux/clk-provider.h | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 25b1734..614444c 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -86,8 +86,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) if (mux->lock) spin_lock_irqsave(mux->lock, flags); - val = readl(mux->reg); - val &= ~(mux->mask << mux->shift); + if (mux->flags & CLK_MUX_HIWORD_MASK) { + val = mux->mask << (mux->shift + 16); + } else { + val = readl(mux->reg); + val &= ~(mux->mask << mux->shift); + } val |= index << mux->shift; writel(val, mux->reg); @@ -111,6 +115,15 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, struct clk_mux *mux; struct clk *clk; struct clk_init_data init; + u8 width = 0; + + if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { + width = fls(mask) - ffs(mask) + 1; + if (width + shift > 16) { + pr_err("mux value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } /* allocate the mux */ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 1186098..fecef88 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -299,6 +299,10 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, * Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) + * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this + * register, and mask of mux bits are in higher 16-bit of this register. + * While setting the mux bits, higher 16-bit should also be updated to + * indicate changing mux bits. */ struct clk_mux { struct clk_hw hw; @@ -312,6 +316,7 @@ struct clk_mux { #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) +#define CLK_MUX_HIWORD_MASK BIT(2) extern const struct clk_ops clk_mux_ops;