From patchwork Sat Jun 8 14:47:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2692561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 3A72A3FC23 for ; Sat, 8 Jun 2013 14:50:16 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UlKRy-00067x-PF; Sat, 08 Jun 2013 14:49:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UlKRa-000796-SE; Sat, 08 Jun 2013 14:48:39 +0000 Received: from mail-pb0-x233.google.com ([2607:f8b0:400e:c01::233]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UlKRW-00077Z-Nk for linux-arm-kernel@lists.infradead.org; Sat, 08 Jun 2013 14:48:35 +0000 Received: by mail-pb0-f51.google.com with SMTP id um15so5714367pbc.24 for ; Sat, 08 Jun 2013 07:48:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=PSA3jocQgmIjCFK8lEmq1jwK7PrQAAXF/qYMtiMQ80U=; b=e2zbmiqkKJ8sH0i+HIRJ3zxQBR8m4t1uBatVyMdnii82+44gQnKjCNt6cvFUp1vNAY hPEYkRGNxYoWMUXG9ot5i5ouZBJlvhd/ClStdfVqjUffnIX0VVFS5z3UuBOmohb4+J72 n/4HcxMDtnOabkWTdBOv8H3rRMKdtprZnISCvyZYyUevBkjIFOjnmdkPdmQj6IyucNof rXx2oCGgaMcx7Lm3ARRPexBNWJmnwKWW1juF5Gewagl6y/FI3URz8CLrgdBGmog1Iabz e5UCe1+ij7iYZ7aDSU2G/LvHSyljkUBnrGawxMQhQqj1FRe4yYQbQ6ZWgo2fp4rIebKG 9g5A== X-Received: by 10.68.108.163 with SMTP id hl3mr3040493pbb.160.1370702891039; Sat, 08 Jun 2013 07:48:11 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id rn7sm3320951pbc.12.2013.06.08.07.47.58 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 08 Jun 2013 07:48:10 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, john.stultz@linaro.org, mturquette@linaro.org, heiko@sntech.de Subject: [PATCH v4 2/7] clk: divider: add CLK_DIVIDER_HIWORD_MASK flag Date: Sat, 8 Jun 2013 22:47:18 +0800 Message-Id: <1370702843-27172-3-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> References: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQlNlz5HrCjnJU6btV5DDzzBVySUgi3MwABotcoUlq4hS1CF+e9CIqkwxJ+z95lZQbncXkkJ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130608_104835_175885_BFA7D4DE X-CRM114-Status: GOOD ( 15.10 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner Signed-off-by: Haojian Zhuang --- drivers/clk/clk-divider.c | 15 +++++++++++++-- include/linux/clk-provider.h | 5 +++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 6d96741..ce5cfe9 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -217,8 +217,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->lock) spin_lock_irqsave(divider->lock, flags); - val = readl(divider->reg); - val &= ~(div_mask(divider) << divider->shift); + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + val = div_mask(divider) << (divider->shift + 16); + } else { + val = readl(divider->reg); + val &= ~(div_mask(divider) << divider->shift); + } val |= value << divider->shift; writel(val, divider->reg); @@ -245,6 +249,13 @@ static struct clk *_register_divider(struct device *dev, const char *name, struct clk *clk; struct clk_init_data init; + if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { + if (width + shift > 16) { + pr_warn("divider value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + /* allocate the divider */ div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); if (!div) { diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index fecef88..8e45fd9 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -257,6 +257,10 @@ struct clk_div_table { * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). + * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit + * of this register, and mask of divider bits are in higher 16-bit of this + * register. While setting the divider bits, higher 16-bit should also be + * updated to indicate changing divider bits. */ struct clk_divider { struct clk_hw hw; @@ -271,6 +275,7 @@ struct clk_divider { #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) extern const struct clk_ops clk_divider_ops; struct clk *clk_register_divider(struct device *dev, const char *name,