From patchwork Sat Jun 8 14:47:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2692571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id B37783FC23 for ; Sat, 8 Jun 2013 14:50:48 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UlKSM-0006Eo-GY; Sat, 08 Jun 2013 14:49:27 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UlKRp-00079r-Lc; Sat, 08 Jun 2013 14:48:54 +0000 Received: from mail-pa0-f45.google.com ([209.85.220.45]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UlKRk-00078Z-Ro for linux-arm-kernel@lists.infradead.org; Sat, 08 Jun 2013 14:48:49 +0000 Received: by mail-pa0-f45.google.com with SMTP id bi5so3266193pad.18 for ; Sat, 08 Jun 2013 07:48:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=sM2lZSgB3Jvsxrf1hPG8qe+AClWSZpnVu3LAGe8+VIQ=; b=QnZK/3JjGF/r4TTAEi6fIEyb7s8nYWZXnO8GN2qXCqoZrkPhSvAjoa+uv9O7TRL2Pr bdoP9MAclAqDdIle6mRTTjBvezNXz5/QCFSvC9zKOpSJNo7PFa42bZ2FyBGxFx11kcqA pgDnLTzPNsamPbotx4j5y2o2uMm8ysT8X8QhpyQy74wPGyMKTKQ//2OcH8nDk89TdhkI S0uLmw7ST8CI+kvoUNRVG9mPnQTIN+RzJVD3sWZmzL9sk5FVPHhlgAZtlAR8k99wAEe6 luu0R02XLsZ1/QKFCQvMvyOkxIs7nmEQcgm8vL35AAJT+JKeDyaQfVySyiGmsY6NgwR0 TLhw== X-Received: by 10.66.159.195 with SMTP id xe3mr7228479pab.49.1370702903397; Sat, 08 Jun 2013 07:48:23 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id rn7sm3320951pbc.12.2013.06.08.07.48.11 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 08 Jun 2013 07:48:22 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, john.stultz@linaro.org, mturquette@linaro.org, heiko@sntech.de Subject: [PATCH v4 3/7] clk: gate: add CLK_GATE_HIWORD_MASK Date: Sat, 8 Jun 2013 22:47:19 +0800 Message-Id: <1370702843-27172-4-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> References: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQkYn3Ao5PRhbnXycvaP6AEQ4qYkuGWarJhoqmnGZ4Fy5oQ0kGuzALf2AwenGbCYFrHpkgTx X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130608_104849_413526_D9FDF1D0 X-CRM114-Status: GOOD ( 15.87 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.45 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16). The patch adds gate flag for this usage. Signed-off-by: Heiko Stuebner Signed-off-by: Haojian Zhuang --- drivers/clk/clk-gate.c | 25 +++++++++++++++++++------ include/linux/clk-provider.h | 5 +++++ 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 15114fe..790306e 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -53,12 +53,18 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) if (gate->lock) spin_lock_irqsave(gate->lock, flags); - reg = readl(gate->reg); - - if (set) - reg |= BIT(gate->bit_idx); - else - reg &= ~BIT(gate->bit_idx); + if (gate->flags & CLK_GATE_HIWORD_MASK) { + reg = BIT(gate->bit_idx + 16); + if (set) + reg |= BIT(gate->bit_idx); + } else { + reg = readl(gate->reg); + + if (set) + reg |= BIT(gate->bit_idx); + else + reg &= ~BIT(gate->bit_idx); + } writel(reg, gate->reg); @@ -121,6 +127,13 @@ struct clk *clk_register_gate(struct device *dev, const char *name, struct clk *clk; struct clk_init_data init; + if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { + if (bit_idx > 16) { + pr_err("gate bit exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + /* allocate the gate */ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); if (!gate) { diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 8e45fd9..8418b6f 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -210,6 +210,10 @@ void of_fixed_clk_setup(struct device_node *np); * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to * enable the clock. Setting this flag does the opposite: setting the bit * disable the clock and clearing it enables the clock + * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit + * of this register, and mask of gate bits are in higher 16-bit of this + * register. While setting the gate bits, higher 16-bit should also be + * updated to indicate changing gate bits. */ struct clk_gate { struct clk_hw hw; @@ -220,6 +224,7 @@ struct clk_gate { }; #define CLK_GATE_SET_TO_DISABLE BIT(0) +#define CLK_GATE_HIWORD_MASK BIT(1) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name,