From patchwork Fri Jun 14 09:35:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: avinash philip X-Patchwork-Id: 2720791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1AD44C0AB1 for ; Fri, 14 Jun 2013 09:37:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 320A32021C for ; Fri, 14 Jun 2013 09:37:02 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB2222021B for ; Fri, 14 Jun 2013 09:37:00 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UnQQR-0006FN-9A; Fri, 14 Jun 2013 09:36:08 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UnQPs-0002dz-1j; Fri, 14 Jun 2013 09:35:32 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UnQPo-0002de-G5 for linux-arm-kernel@lists.infradead.org; Fri, 14 Jun 2013 09:35:29 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r5E9Z0eL026091; Fri, 14 Jun 2013 04:35:00 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r5E9Z0jP001637; Fri, 14 Jun 2013 04:35:00 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Fri, 14 Jun 2013 04:34:59 -0500 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with SMTP id r5E9YuJa022757; Fri, 14 Jun 2013 04:34:57 -0500 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id ECB92158002; Fri, 14 Jun 2013 15:04:55 +0530 (IST) Received: from ubuntu-psp-linux.india.ext.ti.com (ubuntu-psp-linux [192.168.247.46]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r5E9YtR07687; Fri, 14 Jun 2013 15:04:55 +0530 (IST) From: Philip Avinash To: , , , , Subject: [PATCH v2 1/7] gpio: davinci: coding style correction Date: Fri, 14 Jun 2013 15:05:26 +0530 Message-ID: <1371202532-14628-2-git-send-email-avinashphilip@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1371202532-14628-1-git-send-email-avinashphilip@ti.com> References: <1371202532-14628-1-git-send-email-avinashphilip@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130614_053529_253706_1171D283 X-CRM114-Status: GOOD ( 10.54 ) X-Spam-Score: -7.3 (-------) Cc: davinci-linux-open-source@linux.davincidsp.com, avinashphilip@ti.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Make some minor coding style fixes. Use proper multi-line commenting style, arrange include files alphabetically use macros for bit definitions. Signed-off-by: Philip Avinash Signed-off-by: Sekhar Nori --- Changes since v1: - Remove variable name replacement - Add line break after BINTEN macro definition drivers/gpio/gpio-davinci.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 17df6db..e8d189c 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -9,12 +9,12 @@ * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ -#include -#include -#include + #include -#include +#include +#include #include +#include #include @@ -31,6 +31,8 @@ struct davinci_gpio_regs { u32 intstat; }; +#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ + #define chip2controller(chip) \ container_of(chip, struct davinci_gpio_controller, chip) @@ -304,7 +306,8 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) { struct davinci_soc_info *soc_info = &davinci_soc_info; - /* NOTE: we assume for now that only irqs in the first gpio_chip + /* + * NOTE: we assume for now that only irqs in the first gpio_chip * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). */ if (offset < soc_info->gpio_unbanked) @@ -368,7 +371,8 @@ static int __init davinci_gpio_irq_setup(void) } clk_prepare_enable(clk); - /* Arrange gpio_to_irq() support, handling either direct IRQs or + /* + * Arrange gpio_to_irq() support, handling either direct IRQs or * banked IRQs. Having GPIOs in the first GPIO bank use direct * IRQs, while the others use banked IRQs, would need some setup * tweaks to recognize hardware which can do that. @@ -450,10 +454,11 @@ static int __init davinci_gpio_irq_setup(void) } done: - /* BINTEN -- per-bank interrupt enable. genirq would also let these + /* + * BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ - __raw_writel(binten, gpio_base + 0x08); + __raw_writel(binten, gpio_base + BINTEN); printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));