From patchwork Fri Jun 14 14:41:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 2721971 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 754779F8E4 for ; Fri, 14 Jun 2013 14:42:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2863320298 for ; Fri, 14 Jun 2013 14:42:16 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C61C320278 for ; Fri, 14 Jun 2013 14:42:14 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UnVCc-0000ny-O3; Fri, 14 Jun 2013 14:42:11 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UnVCa-0001Fg-13; Fri, 14 Jun 2013 14:42:08 +0000 Received: from mail-pb0-x22d.google.com ([2607:f8b0:400e:c01::22d]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UnVCW-0001FA-AH for linux-arm-kernel@lists.infradead.org; Fri, 14 Jun 2013 14:42:05 +0000 Received: by mail-pb0-f45.google.com with SMTP id mc8so635850pbc.32 for ; Fri, 14 Jun 2013 07:41:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=9zj0Nwpbhrj+LFBtns43Df2ERD5ZzI71yMhO1q1w+qY=; b=MBV3egNbF9L9eFFHr4cyhhI9e4cqGMqXF/Qhv7+IMjQvTDIRIf4TIyQdbl/rc7fzl6 dnIb/OYm8nJGB9YhxAFE4X5vbzGnXJb6umliAEWE5RAyniMwKUMwpuDYX4I7PLDy9Rn7 bok5O4hXSfyGwci6B47gPPpy5rgscMYoj9iB/Wc9YrwKumHNFnO08BFpJu0863lwpIlF wk30PjegGg3LKT8BUVtktn83l4CdH8i4s7KXNNxlqq8+URCaFSBjOrvL5MurB5A/gnL0 +65Yr+igHSITKYQ3XA/kG8CTPeVnP6sWtBqProkSxbQBTljksFzLBVcR0MNE2XXTwavA Awjg== X-Received: by 10.66.121.108 with SMTP id lj12mr2909433pab.52.1371220900537; Fri, 14 Jun 2013 07:41:40 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id v7sm2514979pbq.32.2013.06.14.07.41.37 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 14 Jun 2013 07:41:39 -0700 (PDT) From: Chander Kashyap To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: DT: Exynos: fix number of interrupt-cells in mct node Date: Fri, 14 Jun 2013 20:11:26 +0530 Message-Id: <1371220886-11616-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQnjfcdrvAedLccnx2v7H8NNhYfnxiMRpSxOxhl9FIVEk9/wkECoUutDJR8uHwSfsQaOBjF+ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130614_104204_535071_D4E11ED6 X-CRM114-Status: UNSURE ( 8.08 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) Cc: kgene.kim@samsung.com, t.figa@samsung.com, linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com, Chander Kashyap X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Two cells were used to specify interrupts in mct node, while second cell always remains unused. Hence use only one cell. Suggested by Tomasz Figa. Signed-off-by: Chander Kashyap --- arch/arm/boot/dts/exynos4210.dtsi | 19 +++++++++---------- arch/arm/boot/dts/exynos4212.dtsi | 19 +++++++++---------- arch/arm/boot/dts/exynos4412.dtsi | 23 +++++++++++------------ arch/arm/boot/dts/exynos5250.dtsi | 19 +++++++++---------- 4 files changed, 38 insertions(+), 42 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 54710de..ad50010 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -52,23 +52,22 @@ compatible = "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; interrupt-controller; - #interrups-cells = <2>; + #interrups-cells = <1>; interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; clocks = <&clock 3>, <&clock 344>; clock-names = "fin_pll", "mct"; mct_map: mct-map { - #interrupt-cells = <2>; + #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &gic 0 69 0>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 0 42 0>, - <0x5 0 &gic 0 48 0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &gic 0 69 0>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 0 42 0>, + <5 &gic 0 48 0>; }; }; diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index c0f60f4..ba9ada1 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -39,21 +39,20 @@ compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; interrupt-controller; - #interrups-cells = <2>; + #interrups-cells = <1>; interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; mct_map: mct-map { - #interrupt-cells = <2>; + #interrupt-cells = <>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &combiner 12 5>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 1 12 0>, + <5 &gic 1 12 0>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 270b389..a680de7 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -39,25 +39,24 @@ compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; interrupt-controller; - #interrups-cells = <2>; + #interrups-cells = <1>; interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; clocks = <&clock 3>, <&clock 344>; clock-names = "fin_pll", "mct"; mct_map: mct-map { - #interrupt-cells = <2>; + #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>, - <0x6 0 &gic 1 12 0>, - <0x7 0 &gic 1 12 0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &combiner 12 5>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 1 12 0>, + <5 &gic 1 12 0>, + <6 &gic 1 12 0>, + <7 &gic 1 12 0>; }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index a7cf3f5..4e633ef 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -94,23 +94,22 @@ compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; - #interrups-cells = <2>; + #interrups-cells = <1>; interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; clocks = <&clock 1>, <&clock 335>; clock-names = "fin_pll", "mct"; mct_map: mct-map { - #interrupt-cells = <2>; + #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0x0 0 &combiner 23 3>, - <0x1 0 &combiner 23 4>, - <0x2 0 &combiner 25 2>, - <0x3 0 &combiner 25 3>, - <0x4 0 &gic 0 120 0>, - <0x5 0 &gic 0 121 0>; + interrupt-map = <0 &combiner 23 3>, + <1 &combiner 23 4>, + <2 &combiner 25 2>, + <3 &combiner 25 3>, + <4 &gic 0 120 0>, + <5 &gic 0 121 0>; }; };