| Message ID | 1371828605-18053-4-git-send-email-lho@apm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 21, 2013 at 04:30:05PM +0100, Loc Ho wrote: > Documentation: Add documentation for APM X-Gene clock binding with PLL and > device clocks. > > Signed-off-by: Loc Ho <lho@apm.com> > Signed-off-by: Kumar Sankaran <ksankaran@apm.com> > Signed-off-by: Vinayak Kale <vkale@apm.com> > Signed-off-by: Feng Kan <fkan@apm.com> > --- > Documentation/devicetree/bindings/clock/xgene.txt | 90 +++++++++++++++++++++ > 1 files changed, 90 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/xgene.txt > > diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt > new file mode 100644 > index 0000000..fcdee79 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xgene.txt > @@ -0,0 +1,90 @@ > +Device Tree Clock bindings for APM X-Gene > + > +This binding uses the common clock binding[1]. > + > +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt > + > +Required properties: > +- compatible : shall be one of the following: > + "apm,xgene-pll-clock" - for a X-Gene PLL clock > + "apm,xgene-device-clock" - for a X-Gene device clock > + > +Required properties for PLL clocks: > +- reg : shall be the physical PLL register address for the pll clock. > +- clocks : shall be the input parent clock phandle for the clock. This should > + be the reference clock. > +- #clock-cells : shall be set to 1. > +- clock-output-names : shall be the name of the PLL referenced by derive > + clock. > +- type : shall be 1 for SoC PLL and 0 for PCP PLL. That makes the binding very difficult for a human to read, could this not be part of the compatible string? e.g. "apm,xgene-pcp-pll-clock". > +Optional properties for PLL clocks: > +- clock-names : shall be the name of the PLL. If missing, use the device name. > + > +Required properties for device clocks: > +- reg : shall be the physical CSR reset address base and physical CSR divider > + address base. If one does not exist, specify 0 for address and 0 for > + size. > +- clocks : shall be the input parent clock phandle for the clock. > +- #clock-cells : shall be set to 1. > +- clock-output-names : shall be the name of the device referenced. > +Optional properties for device clocks: > +- clock-names : shall be the name of the device clock. If missing, use the > + device name. > +- flags : Any clock flags. ie. use 0x8 to leave clock un-touch if not > + referenced. Default is 0. What flags are these? We should *not* be exporting Linux-internal flags as devicetree bindings. > +- csr-offset : Offset to the CSR reset register from the reset address base. > + Default is 0. > +- csr-mask : CSR reset mask bit. Default is 0xF. > +- enable-offset : Offset to the enable register from the reset address base. > + Default is 0x8. > +- enable-mask : CSR enable mask bit. Default is 0xF. > +- divider-offset : Offset to the divider CSR register from the divider base. > + Default is 0x0. > +- divider-width : Width of the divider register. Default is 0. > +- divider-shift : Bit shift of the divider register. Default is 0. > + > +For example: > + > + pcppll: pcppll@17000100 { > + compatible = "apm,xgene-pll-clock"; > + #clock-cells = <1>; > + clocks = <&refclk 0>; > + clock-names = "pcppll"; > + reg = <0x0 0x17000100 0x0 0x1000>; > + clock-output-names = "pcppll"; > + type = <0>; > + }; > + > + socpll: socpll@17000120 { > + compatible = "apm,xgene-pll-clock"; > + #clock-cells = <1>; > + clocks = <&refclk 0>; > + clock-names = "socpll"; > + reg = <0x0 0x17000120 0x0 0x1000>; > + clock-output-names = "socpll"; > + type = <1>; > + }; > + > + qmlclk: qmlclk { > + compatible = "apm,xgene-device-clock"; > + #clock-cells = <1>; > + clocks = <&socplldiv2 0>; > + clock-names = "qmlclk"; > + reg = <0x0 0x1703C000 0x0 0x1000 > + 0x0 0x00000000 0x0 0x0000>; > + clock-output-names = "qmlclk"; > + }; > + > + ethclk: ethclk { > + compatible = "apm,xgene-device-clock"; > + #clock-cells = <1>; > + clocks = <&socplldiv2 0>; > + clock-names = "ethclk"; > + reg = <0x0 0x00000000 0x0 0x0000 > + 0x0 0x17000000 0x0 0x1000>; > + divider-offset = <0x238>; Extraneous tab here. Thanks, Mark.
HI, >> +Required properties for PLL clocks: >> +- reg : shall be the physical PLL register address for the pll clock. >> +- clocks : shall be the input parent clock phandle for the clock. This should >> + be the reference clock. >> +- #clock-cells : shall be set to 1. >> +- clock-output-names : shall be the name of the PLL referenced by derive >> + clock. >> +- type : shall be 1 for SoC PLL and 0 for PCP PLL. > > That makes the binding very difficult for a human to read, could this not be > part of the compatible string? e.g. "apm,xgene-pcp-pll-clock". [Loc Ho] I guess I could by they will only differ by one function in term of rate computation. > >> +Optional properties for PLL clocks: >> +- clock-names : shall be the name of the PLL. If missing, use the device name. >> + >> +Required properties for device clocks: >> +- reg : shall be the physical CSR reset address base and physical CSR divider >> + address base. If one does not exist, specify 0 for address and 0 for >> + size. >> +- clocks : shall be the input parent clock phandle for the clock. >> +- #clock-cells : shall be set to 1. >> +- clock-output-names : shall be the name of the device referenced. >> +Optional properties for device clocks: >> +- clock-names : shall be the name of the device clock. If missing, use the >> + device name. >> +- flags : Any clock flags. ie. use 0x8 to leave clock un-touch if not >> + referenced. Default is 0. > > What flags are these? We should *not* be exporting Linux-internal flags as > devicetree bindings. [Loc Ho] I need the CLK ignore if un-used. This is needed in case an subsystem - such as PCIE is NOT powered on. With different board design, some IP may not have power. Accessing the clock registers will cause exception in the kernel. I guess I could just add the clock IGNORE by default and not require this. -Loc
On Mon, Jun 24, 2013 at 06:57:14PM +0100, Loc Ho wrote: > HI, > > > >> +Required properties for PLL clocks: > >> +- reg : shall be the physical PLL register address for the pll clock. > >> +- clocks : shall be the input parent clock phandle for the clock. This should > >> + be the reference clock. > >> +- #clock-cells : shall be set to 1. > >> +- clock-output-names : shall be the name of the PLL referenced by derive > >> + clock. > >> +- type : shall be 1 for SoC PLL and 0 for PCP PLL. > > > > That makes the binding very difficult for a human to read, could this not be > > part of the compatible string? e.g. "apm,xgene-pcp-pll-clock". > [Loc Ho] > I guess I could by they will only differ by one function in term of > rate computation. Having a clear binding is useful, and it's just as easy to do a comparison on the compatible string as it is to deal with the an opaque type parameter. Another option would be to make the type parameter a string (i.e type = "soc" or type = "pcp"), if you feel that they are similar enough to not warrant separate bindings. > > > > >> +Optional properties for PLL clocks: > >> +- clock-names : shall be the name of the PLL. If missing, use the device name. > >> + > >> +Required properties for device clocks: > >> +- reg : shall be the physical CSR reset address base and physical CSR divider > >> + address base. If one does not exist, specify 0 for address and 0 for > >> + size. > >> +- clocks : shall be the input parent clock phandle for the clock. > >> +- #clock-cells : shall be set to 1. > >> +- clock-output-names : shall be the name of the device referenced. > >> +Optional properties for device clocks: > >> +- clock-names : shall be the name of the device clock. If missing, use the > >> + device name. > >> +- flags : Any clock flags. ie. use 0x8 to leave clock un-touch if not > >> + referenced. Default is 0. > > > > What flags are these? We should *not* be exporting Linux-internal flags as > > devicetree bindings. > [Loc Ho] > I need the CLK ignore if un-used. This is needed in case an subsystem > - such as PCIE is NOT powered on. With different board design, some IP > may not have power. Accessing the clock registers will cause exception > in the kernel. I guess I could just add the clock IGNORE by default > and not require this. In cases where the clocks (or any devices) are unusable on a system for some reason (e.g. they are unpowered), you could instead set their status property to "disabled" in a board-specific dts to describe this (or deafualt them to "disabled" and override this to "okay" in a board file). That's the conventional way of doing it, and there's already framework for this in the kernel that prevents them from getting probed (though I'm not enitrely sure if this is the case when using *_OF_DECLARE). Thanks, Mark.
Hi, >> >> +Required properties for PLL clocks: >> >> +- reg : shall be the physical PLL register address for the pll clock. >> >> +- clocks : shall be the input parent clock phandle for the clock. This should >> >> + be the reference clock. >> >> +- #clock-cells : shall be set to 1. >> >> +- clock-output-names : shall be the name of the PLL referenced by derive >> >> + clock. >> >> +- type : shall be 1 for SoC PLL and 0 for PCP PLL. >> > >> > That makes the binding very difficult for a human to read, could this not be >> > part of the compatible string? e.g. "apm,xgene-pcp-pll-clock". >> [Loc Ho] >> I guess I could by they will only differ by one function in term of >> rate computation. > > Having a clear binding is useful, and it's just as easy to do a > comparison on the compatible string as it is to deal with the an opaque > type parameter. Another option would be to make the type parameter a > string (i.e type = "soc" or type = "pcp"), if you feel that they are > similar enough to not warrant separate bindings. [Loc Ho] I just create two binding type. And just set the type parameter based on binding. >> >> +Optional properties for PLL clocks: >> >> +- clock-names : shall be the name of the PLL. If missing, use the device name. >> >> + >> >> +Required properties for device clocks: >> >> +- reg : shall be the physical CSR reset address base and physical CSR divider >> >> + address base. If one does not exist, specify 0 for address and 0 for >> >> + size. >> >> +- clocks : shall be the input parent clock phandle for the clock. >> >> +- #clock-cells : shall be set to 1. >> >> +- clock-output-names : shall be the name of the device referenced. >> >> +Optional properties for device clocks: >> >> +- clock-names : shall be the name of the device clock. If missing, use the >> >> + device name. >> >> +- flags : Any clock flags. ie. use 0x8 to leave clock un-touch if not >> >> + referenced. Default is 0. >> > >> > What flags are these? We should *not* be exporting Linux-internal flags as >> > devicetree bindings. >> [Loc Ho] >> I need the CLK ignore if un-used. This is needed in case an subsystem >> - such as PCIE is NOT powered on. With different board design, some IP >> may not have power. Accessing the clock registers will cause exception >> in the kernel. I guess I could just add the clock IGNORE by default >> and not require this. > > In cases where the clocks (or any devices) are unusable on a system for > some reason (e.g. they are unpowered), you could instead set their > status property to "disabled" in a board-specific dts to describe this > (or deafualt them to "disabled" and override this to "okay" in a board > file). That's the conventional way of doing it, and there's already > framework for this in the kernel that prevents them from getting probed > (though I'm not enitrely sure if this is the case when using > *_OF_DECLARE). [Loc Ho] We are doing this. Though, this requires two set of DTS file and/or patching the DTS from U-Boot or BIOS. I am trying to avoid having multiple DTS file and having to write patching code. -Loc
diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt new file mode 100644 index 0000000..fcdee79 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xgene.txt @@ -0,0 +1,90 @@ +Device Tree Clock bindings for APM X-Gene + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "apm,xgene-pll-clock" - for a X-Gene PLL clock + "apm,xgene-device-clock" - for a X-Gene device clock + +Required properties for PLL clocks: +- reg : shall be the physical PLL register address for the pll clock. +- clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the PLL referenced by derive + clock. +- type : shall be 1 for SoC PLL and 0 for PCP PLL. +Optional properties for PLL clocks: +- clock-names : shall be the name of the PLL. If missing, use the device name. + +Required properties for device clocks: +- reg : shall be the physical CSR reset address base and physical CSR divider + address base. If one does not exist, specify 0 for address and 0 for + size. +- clocks : shall be the input parent clock phandle for the clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the device referenced. +Optional properties for device clocks: +- clock-names : shall be the name of the device clock. If missing, use the + device name. +- flags : Any clock flags. ie. use 0x8 to leave clock un-touch if not + referenced. Default is 0. +- csr-offset : Offset to the CSR reset register from the reset address base. + Default is 0. +- csr-mask : CSR reset mask bit. Default is 0xF. +- enable-offset : Offset to the enable register from the reset address base. + Default is 0x8. +- enable-mask : CSR enable mask bit. Default is 0xF. +- divider-offset : Offset to the divider CSR register from the divider base. + Default is 0x0. +- divider-width : Width of the divider register. Default is 0. +- divider-shift : Bit shift of the divider register. Default is 0. + +For example: + + pcppll: pcppll@17000100 { + compatible = "apm,xgene-pll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "pcppll"; + reg = <0x0 0x17000100 0x0 0x1000>; + clock-output-names = "pcppll"; + type = <0>; + }; + + socpll: socpll@17000120 { + compatible = "apm,xgene-pll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "socpll"; + reg = <0x0 0x17000120 0x0 0x1000>; + clock-output-names = "socpll"; + type = <1>; + }; + + qmlclk: qmlclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "qmlclk"; + reg = <0x0 0x1703C000 0x0 0x1000 + 0x0 0x00000000 0x0 0x0000>; + clock-output-names = "qmlclk"; + }; + + ethclk: ethclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "ethclk"; + reg = <0x0 0x00000000 0x0 0x0000 + 0x0 0x17000000 0x0 0x1000>; + divider-offset = <0x238>; + divider-width = <0x9>; + divider-shift = <0x0>; + clock-output-names = "ethclk"; + }; +