From patchwork Mon Jun 24 22:34:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loc Ho X-Patchwork-Id: 2773901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BE9179F245 for ; Mon, 24 Jun 2013 22:37:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C7B3C20231 for ; Mon, 24 Jun 2013 22:37:39 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B984200ED for ; Mon, 24 Jun 2013 22:37:38 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UrFMV-0006F5-BR; Mon, 24 Jun 2013 22:35:52 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UrFMC-00079Q-0m; Mon, 24 Jun 2013 22:35:32 +0000 Received: from exprod5og109.obsmtp.com ([64.18.0.188]) by merlin.infradead.org with smtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UrFLm-00075e-Rn for linux-arm-kernel@lists.infradead.org; Mon, 24 Jun 2013 22:35:08 +0000 Received: from mail-pa0-f50.google.com ([209.85.220.50]) (using TLSv1) by exprod5ob109.postini.com ([64.18.4.12]) with SMTP ID DSNKUcjJizjxqlwdHGQG27nr55P8197rmycB@postini.com; Mon, 24 Jun 2013 15:35:06 PDT Received: by mail-pa0-f50.google.com with SMTP id fb1so11723265pad.37 for ; Mon, 24 Jun 2013 15:34:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=P3b7iTpJGmDrG9kHgqU4uv9vygJ+JjL+UotMTt7X/1k=; b=X0yZLWPjsIBu7aN7/HSRQmwS+d+SxSh9edNPwCv2V04Xml7sFy+xV3zc2xlUIikufT 5Vh5bC2u86PYF/yUeG7dCyyAOqSGfDJ1oHOxqPrLNj0XHBc+f7EWluP6emwt39PUDz/n VK5PzER9yQPv2zV/tIIe9TvtfVIq+Dg7mGcmrwJ2e0y0UHV9IOlZh/8Z8MLWDDz4ASnS nOXrQHCwCemKJ8Y2j1vfoMLi6S/YcO0dIt4Vqog/tchvCD885fImfYcRr6Jcbg9nJAVJ 50aYnZFM+Ou2r/6EwCvMZWFDyfcI1DQhpg+i9b6qxmdvNYKbG/9CRaoUgubaMK3b567P w0eg== X-Received: by 10.68.36.230 with SMTP id t6mr7642431pbj.15.1372113290705; Mon, 24 Jun 2013 15:34:50 -0700 (PDT) X-Received: by 10.68.36.230 with SMTP id t6mr7642422pbj.15.1372113290640; Mon, 24 Jun 2013 15:34:50 -0700 (PDT) Received: from localhost ([198.137.200.11]) by mx.google.com with ESMTPSA id ix3sm19932330pbc.37.2013.06.24.15.34.48 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 24 Jun 2013 15:34:49 -0700 (PDT) From: Loc Ho To: mark.rutland@arm.com Subject: [PATCH v4 3/3] Documentation: Add documentation for APM X-Gene clock binding Date: Mon, 24 Jun 2013 16:34:23 -0600 Message-Id: <1372113263-18082-4-git-send-email-lho@apm.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1372113263-18082-3-git-send-email-lho@apm.com> References: <1372113263-18082-1-git-send-email-lho@apm.com> <1372113263-18082-2-git-send-email-lho@apm.com> <1372113263-18082-3-git-send-email-lho@apm.com> X-Gm-Message-State: ALoCoQmqybPi6Cu8YjzvqqJcJoztNIWkvsi/ACjQJtAh0Y7Q/O5yV1M1znctWbzdVX4iFI/e6p849eltX9/jjpH+S78cc1t2nREBPRfOmvLt1U++5Jg4aQ6VNEsseG3LjPVX3qMiRpOEgmydu61h8XQ0waGbkUji7xlVH4VDJVbTOARYL3ovs9vsrYZBhMso6L0UvLHQBqbC X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130624_183507_152347_0F2FD295 X-CRM114-Status: GOOD ( 11.46 ) X-Spam-Score: -4.2 (----) Cc: fkan@apm.com, mturquette@linaro.org, Catalin.Marinas@arm.com, Loc Ho , ksankaran@apm.com, vkale@apm.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Documentation: Add documentation for APM X-Gene clock binding with PLL and device clocks. Signed-off-by: Loc Ho Signed-off-by: Kumar Sankaran Signed-off-by: Vinayak Kale Signed-off-by: Feng Kan --- Documentation/devicetree/bindings/clock/xgene.txt | 109 +++++++++++++++++++++ 1 files changed, 109 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xgene.txt diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt new file mode 100644 index 0000000..cda90f1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xgene.txt @@ -0,0 +1,109 @@ +Device Tree Clock bindings for APM X-Gene + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock + "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock + "apm,xgene-device-clock" - for a X-Gene device clock + +Required properties for SoC or PCP PLL clocks: +- reg : shall be the physical PLL register address for the pll clock. +- clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the PLL referenced by derive + clock. +Optional properties for PLL clocks: +- clock-names : shall be the name of the PLL. If missing, use the device name. + +Required properties for device clocks: +- reg : shall be the physical CSR reset address base and/or physical CSR + divider address base if one existed. +- reg-names : shall be string describing the reg resource. Supported + register names are "csr-reg" and "div-reg" which default + to "csr-reg" if not specified. +- clocks : shall be the input parent clock phandle for the clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the device referenced. +Optional properties for device clocks: +- clock-names : shall be the name of the device clock. If missing, use the + device name. +- csr-offset : Offset to the CSR reset register from the reset address base. + Default is 0. +- csr-mask : CSR reset mask bit. Default is 0xF. +- enable-offset : Offset to the enable register from the reset address base. + Default is 0x8. +- enable-mask : CSR enable mask bit. Default is 0xF. +- divider-offset : Offset to the divider CSR register from the divider base. + Default is 0x0. +- divider-width : Width of the divider register. Default is 0. +- divider-shift : Bit shift of the divider register. Default is 0. + +For example: + + pcppll: pcppll@17000100 { + compatible = "apm,xgene-pcppll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "pcppll"; + reg = <0x0 0x17000100 0x0 0x1000>; + clock-output-names = "pcppll"; + type = <0>; + }; + + socpll: socpll@17000120 { + compatible = "apm,xgene-socpll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "socpll"; + reg = <0x0 0x17000120 0x0 0x1000>; + clock-output-names = "socpll"; + type = <1>; + }; + + qmlclk: qmlclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "qmlclk"; + reg = <0x0 0x1703C000 0x0 0x1000>; + reg-name = "csr-reg"; + clock-output-names = "qmlclk"; + }; + + ethclk: ethclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "ethclk"; + reg = <0x0 0x17000000 0x0 0x1000>; + reg-names = "div-reg"; + divider-offset = <0x238>; + divider-width = <0x9>; + divider-shift = <0x0>; + clock-output-names = "ethclk"; + }; + + apbclk: apbclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&ahbclk 0>; + clock-names = "apbclk"; + reg = <0x0 0x1F2AC000 0x0 0x1000 + 0x0 0x1F2AC000 0x0 0x1000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x200>; + enable-offset = <0x8>; + enable-mask = <0x200>; + divider-offset = <0x10>; + divider-width = <0x2>; + divider-shift = <0x0>; + flags = <0x8>; + clock-output-names = "apbclk"; + }; +