From patchwork Tue Jun 25 09:24:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 2775551 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E7858C0AB1 for ; Tue, 25 Jun 2013 09:32:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BE559201D0 for ; Tue, 25 Jun 2013 09:32:12 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5C1EA2012D for ; Tue, 25 Jun 2013 09:32:11 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UrPYt-0005F1-1W; Tue, 25 Jun 2013 09:29:21 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UrPY9-0000jG-4a; Tue, 25 Jun 2013 09:28:33 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UrPXX-0000eN-Tu for linux-arm-kernel@lists.infradead.org; Tue, 25 Jun 2013 09:27:59 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 25 Jun 2013 02:24:19 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 25 Jun 2013 02:22:43 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 25 Jun 2013 02:22:43 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.298.1; Tue, 25 Jun 2013 02:24:27 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH V3 2/3] ARM: tegra114: add low level support for CPU idle powered-down mode Date: Tue, 25 Jun 2013 17:24:01 +0800 Message-ID: <1372152242-16373-4-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1372152242-16373-1-git-send-email-josephl@nvidia.com> References: <1372152242-16373-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130625_052756_165595_20561A29 X-CRM114-Status: GOOD ( 10.58 ) X-Spam-Score: -3.2 (---) Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The flow controller would take care the power sequence when CPU idle in powered-down mode. It powered gate the CPU when CPU runs into WFI instruction. And wake up the CPU when event be triggered. The sequence is below. * setting wfi bitmap for the CPU as the halt event in the FLOW_CTRL_CPU_HALT_REG to monitor the CPU running into WFI,then power gate it * setting IRQ and FIQ as wake up event to wake up CPU when event triggered Signed-off-by: Joseph Lo --- V3: * no change V2: * no change --- arch/arm/mach-tegra/flowctrl.h | 2 ++ arch/arm/mach-tegra/sleep-tegra30.S | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index 7a29bae..e56a950 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h @@ -28,6 +28,8 @@ #define FLOW_CTRL_SCLK_RESUME (1 << 27) #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) +#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) +#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) #define FLOW_CTRL_CPU0_CSR 0x8 #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index ada8821..5877f26 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -99,6 +99,8 @@ flow_ctrl_setting_for_lp2: cmp r10, #TEGRA30 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 movne r3, #FLOW_CTRL_WAITEVENT + orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ + orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ flow_ctrl_done: cmp r10, #TEGRA30 str r3, [r2]