From patchwork Wed Jun 26 09:28:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 2788251 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CAFD5C0AB1 for ; Wed, 26 Jun 2013 20:35:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C705620271 for ; Wed, 26 Jun 2013 20:35:45 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB34020270 for ; Wed, 26 Jun 2013 20:35:44 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UrtD3-0007VI-CN; Wed, 26 Jun 2013 17:08:50 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UrtA8-0001Mc-1V; Wed, 26 Jun 2013 17:05:44 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UrsI9-00037P-33 for linux-arm-kernel@merlin.infradead.org; Wed, 26 Jun 2013 16:09:57 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Urm3g-00041U-H5 for linux-arm-kernel@lists.infradead.org; Wed, 26 Jun 2013 09:30:37 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 26 Jun 2013 02:28:51 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 26 Jun 2013 02:29:22 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 26 Jun 2013 02:29:22 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.298.1; Wed, 26 Jun 2013 02:29:24 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 26 Jun 2013 02:29:23 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r5Q9SmR2017123; Wed, 26 Jun 2013 02:29:22 -0700 (PDT) From: Hiroshi Doyu To: Subject: [PATCH 17/23] iommu/tegra: smmu: Use swgroups instead of pdata Date: Wed, 26 Jun 2013 12:28:20 +0300 Message-ID: <1372238906-9346-18-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130626_103036_945299_41D6DF9F X-CRM114-Status: GOOD ( 15.69 ) X-Spam-Score: -3.2 (---) Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hiroshi Doyu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of using platfrom data, DT passes "nvidia,swgroups". Signed-off-by: Hiroshi Doyu --- drivers/iommu/tegra-smmu.c | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index c67131e..64da08a 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -265,7 +265,7 @@ struct smmu_client { struct device *dev; struct list_head list; struct smmu_as *as; - u32 hwgrp; + u64 hwgrp; }; /* @@ -384,10 +384,10 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) */ #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG) -#define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data) +#define smmu_client_hwgrp(c) (c->as->smmu->swgroups) static int __smmu_client_set_hwgrp(struct smmu_client *c, - unsigned long map, int on) + u64 map, int on) { int i; struct smmu_as *as = c->as; @@ -400,12 +400,11 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, if (!on) map = smmu_client_hwgrp(c); - for_each_set_bit(i, &map, HWGRP_COUNT) { + for_each_set_bit(i, (unsigned long *)&map, + sizeof(map) * BITS_PER_BYTE) { offs = HWGRP_ASID_REG(i); val = smmu_read(smmu, offs); if (on) { - if (WARN_ON(val & mask)) - goto err_hw_busy; val |= mask; } else { WARN_ON((val & mask) == mask); @@ -416,15 +415,6 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, FLUSH_SMMU_REGS(smmu); c->hwgrp = map; return 0; - -err_hw_busy: - for_each_set_bit(i, &map, HWGRP_COUNT) { - offs = HWGRP_ASID_REG(i); - val = smmu_read(smmu, offs); - val &= ~mask; - smmu_write(smmu, val, offs); - } - return -EBUSY; } static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on) @@ -796,7 +786,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain, struct smmu_as *as = domain->priv; struct smmu_device *smmu = as->smmu; struct smmu_client *client, *c; - u32 map; + u64 map; int err; client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL); @@ -804,7 +794,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain, return -ENOMEM; client->dev = dev; client->as = as; - map = (unsigned long)dev->platform_data; + map = smmu->swgroups; if (!map) return -EINVAL;