From patchwork Thu Jun 27 09:47:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 2791261 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8CFEE9F756 for ; Thu, 27 Jun 2013 09:52:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 58C8C202F1 for ; Thu, 27 Jun 2013 09:52:08 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0425D202F0 for ; Thu, 27 Jun 2013 09:52:07 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Us8pi-0000VR-Tz; Thu, 27 Jun 2013 09:49:43 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Us8pA-0003nd-HB; Thu, 27 Jun 2013 09:49:08 +0000 Received: from moutng.kundenserver.de ([212.227.17.9]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Us8oU-0003kf-Lj for linux-arm-kernel@lists.infradead.org; Thu, 27 Jun 2013 09:48:28 +0000 Received: from axis700.grange (dslb-094-221-112-035.pools.arcor-ip.net [94.221.112.35]) by mrelayeu.kundenserver.de (node=mreu0) with ESMTP (Nemesis) id 0MfE46-1UdMoP3wMs-00OuAV; Thu, 27 Jun 2013 11:48:00 +0200 Received: from 6a.grange (6a.grange [192.168.1.11]) by axis700.grange (Postfix) with ESMTPS id 6C7D840BB4; Thu, 27 Jun 2013 11:47:59 +0200 (CEST) Received: from lyakh by 6a.grange with local (Exim 4.72) (envelope-from ) id 1Us8o3-0003us-2L; Thu, 27 Jun 2013 11:47:59 +0200 From: Guennadi Liakhovetski To: linux-sh@vger.kernel.org Subject: [PATCH 1/3] ARM: shmobile: r8a73a4: add clocks for I2C controllers Date: Thu, 27 Jun 2013 11:47:56 +0200 Message-Id: <1372326479-15028-2-git-send-email-g.liakhovetski@gmx.de> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1372326479-15028-1-git-send-email-g.liakhovetski@gmx.de> References: <1372326479-15028-1-git-send-email-g.liakhovetski@gmx.de> X-Provags-ID: V02:K0:tLOTzGEitW0aZBnOFqCDZ9TYeoUW+YGPaPChcncFV56 rmzQZw8mCVo6JUbfZk+Ll8U/2HRCJzn3jU0Ofdf2iCOGm1uzsJ a5CutajyuuZ1b6nI06lGi2gSn/xYW4tB5LRgEDo2nK8NWHSjEq yfrJgMSbafHdAULsTPcpCm9JHfkafjv2Ab+JyKn3fE0OuHjVqT 8QTF4SdvE4skOXFGPkhFudsw346NaE3tC21tLvwA+7PIMjF4oS DFAcx8F53ASHiD7CP+oPUxrrnxqNcAu0RRMxPoaW8arMPTjDGp bJh6yAUYwkEhVwN683aJVu0+1iPJrr2iKE5AFwL7ri0rn0Ymx7 7CwF/QjKINKxEFXwI8Fs6q3P2BjqF6BMu9W+mEGklxu8gzJMQG 7FA/Crl6E4mZw== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130627_054826_917925_C2F86E14 X-CRM114-Status: GOOD ( 12.37 ) X-Spam-Score: -3.2 (---) Cc: Guennadi Liakhovetski , Simon Horman , Magnus Damm , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP r8a73a4 SoCs have numerous I2C controllers, of which 9 are compatible with the i2c-sh_mobile.c driver. This patch adds clock definitions for them. Signed-off-by: Guennadi Liakhovetski Acked-by: Kuninori Morimoto --- arch/arm/mach-shmobile/clock-r8a73a4.c | 25 +++++++++++++++++++++++-- 1 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index cbf9852..508cb1e 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -30,6 +30,7 @@ #define SMSTPCR2 0xe6150138 #define SMSTPCR3 0xe615013c +#define SMSTPCR4 0xe6150140 #define SMSTPCR5 0xe6150144 #define FRQCRA 0xE6150000 @@ -487,8 +488,10 @@ static struct clk div6_clks[DIV6_NR] = { /* MSTP */ enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, - MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, - MSTP522, + MSTP323, MSTP318, MSTP317, MSTP316, + MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, + MSTP411, MSTP410, MSTP409, + MSTP522, MSTP515, MSTP_NR }; @@ -499,12 +502,21 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */ [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ + [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0), /* IIC6 */ + [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */ + [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */ + [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ + [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */ + [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ + [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ + [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0), /* IIC8 */ }; static struct clk_lookup lookups[] = { @@ -549,6 +561,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), + CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), @@ -559,6 +572,14 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]), + CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]), + CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), + CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]), + CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]), + CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]), + CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]), + CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]), /* for DT */ CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),