From patchwork Fri Jul 5 10:44:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 2824105 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9DF51BF4A1 for ; Fri, 5 Jul 2013 10:50:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9EAE7201CB for ; Fri, 5 Jul 2013 10:50:58 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4661B201C8 for ; Fri, 5 Jul 2013 10:50:57 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uv3Xz-00020e-Oy; Fri, 05 Jul 2013 10:47:29 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uv3XO-0004lD-2b; Fri, 05 Jul 2013 10:46:50 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uv3WO-0004X9-Ut for linux-arm-kernel@lists.infradead.org; Fri, 05 Jul 2013 10:45:54 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 05 Jul 2013 03:52:50 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 05 Jul 2013 03:46:26 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 05 Jul 2013 03:46:26 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Fri, 5 Jul 2013 03:45:21 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 05 Jul 2013 03:45:21 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r65AjE3b022328; Fri, 5 Jul 2013 03:45:20 -0700 (PDT) From: Hiroshi Doyu To: Subject: [PATCH v2 03/22] ARM: tegra: Create a DT header defining swgroups ID Date: Fri, 5 Jul 2013 13:44:38 +0300 Message-ID: <1373021097-32420-4-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> References: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130705_064549_365244_E8013B02 X-CRM114-Status: UNSURE ( 9.43 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -7.1 (-------) Cc: linux-tegra@vger.kernel.org, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, Hiroshi Doyu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Create a header file to define the swgroup IDs used by the IOMMU(SMMU) binding. "swgroup" is a group of H/W clients in Tegra SoC from S/W POV. This will allow the same header to be used by both device tree files, and drivers implementing this binding, which guarantees that the two stay in sync. This also makes device trees more readable by using names instead of magic numbers. Signed-off-by: Hiroshi Doyu --- include/dt-bindings/memory/tegra-swgroup.h | 50 ++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 include/dt-bindings/memory/tegra-swgroup.h diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h new file mode 100644 index 0000000..4cfa769 --- /dev/null +++ b/include/dt-bindings/memory/tegra-swgroup.h @@ -0,0 +1,50 @@ +/* + * This header provides constants for binding nvidia,swgroup ID + */ + +#ifndef _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H +#define _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H + +#define TEGRA_SWGROUP_AFI 0 +#define TEGRA_SWGROUP_AVPC 1 +#define TEGRA_SWGROUP_DC 2 +#define TEGRA_SWGROUP_DCB 3 +#define TEGRA_SWGROUP_EPP 4 +#define TEGRA_SWGROUP_G2 5 +#define TEGRA_SWGROUP_HC 6 +#define TEGRA_SWGROUP_HDA 7 +#define TEGRA_SWGROUP_ISP 8 +#define TEGRA_SWGROUP_ISP2 SWGID_ISP +/* UNUSED: 9 */ +/* UNUSED: 10 */ +#define TEGRA_SWGROUP_MPE 11 +#define TEGRA_SWGROUP_MSENC SWGID_MPE +#define TEGRA_SWGROUP_NV 12 +#define TEGRA_SWGROUP_NV2 13 +#define TEGRA_SWGROUP_PPCS 14 +#define TEGRA_SWGROUP_SATA2 15 +#define TEGRA_SWGROUP_SATA 16 +#define TEGRA_SWGROUP_VDE 17 +#define TEGRA_SWGROUP_VI 18 +#define TEGRA_SWGROUP_VIC 19 +#define TEGRA_SWGROUP_XUSB_HOST 20 +#define TEGRA_SWGROUP_XUSB_DEV 21 +#define TEGRA_SWGROUP_A9AVP 22 +#define TEGRA_SWGROUP_TSEC 23 +#define TEGRA_SWGROUP_PPCS1 24 +/* UNUSED: 25 */ +/* UNUSED: 26 */ +/* UNUSED: 27 */ +/* UNUSED: 28 */ +/* UNUSED: 29 */ +/* UNUSED: 30 */ +/* UNUSED: 31 */ + +/* Reserved: 32-63 */ + +#define TEGRA_SWGROUP_BIT(x) (1ULL << TEGRA_SWGROUP_##x) + +#define TEGRA30_SWGROUP_ALL <0x00000000 0x000779ff> +#define TEGRA114_SWGROUP_ALL <0x00000000 0x01b659fe> + +#endif /* _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H */