From patchwork Thu Jul 11 06:27:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Chen X-Patchwork-Id: 2826003 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B6BC49F756 for ; Thu, 11 Jul 2013 06:31:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9B04C20121 for ; Thu, 11 Jul 2013 06:31:48 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 540662013A for ; Thu, 11 Jul 2013 06:31:47 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxANN-0006nx-Io; Thu, 11 Jul 2013 06:29:14 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxAMt-0007DY-8u; Thu, 11 Jul 2013 06:28:43 +0000 Received: from co9ehsobe005.messaging.microsoft.com ([207.46.163.28] helo=co9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxAMN-00077t-JH for linux-arm-kernel@lists.infradead.org; Thu, 11 Jul 2013 06:28:14 +0000 Received: from mail104-co9-R.bigfish.com (10.236.132.253) by CO9EHSOBE027.bigfish.com (10.236.130.90) with Microsoft SMTP Server id 14.1.225.22; Thu, 11 Jul 2013 06:27:54 +0000 Received: from mail104-co9 (localhost [127.0.0.1]) by mail104-co9-R.bigfish.com (Postfix) with ESMTP id 007EB4601BF; Thu, 11 Jul 2013 06:27:54 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e23h1155h) Received: from mail104-co9 (localhost.localdomain [127.0.0.1]) by mail104-co9 (MessageSwitch) id 137352407245595_9306; Thu, 11 Jul 2013 06:27:52 +0000 (UTC) Received: from CO9EHSMHS032.bigfish.com (unknown [10.236.132.232]) by mail104-co9.bigfish.com (Postfix) with ESMTP id 06C43200062; Thu, 11 Jul 2013 06:27:52 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS032.bigfish.com (10.236.130.42) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 11 Jul 2013 06:27:51 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.136.1; Thu, 11 Jul 2013 06:30:04 +0000 Received: from localhost.localdomain (nchen-desktop.ap.freescale.net [10.192.242.40]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r6B6RLD7016369; Wed, 10 Jul 2013 23:27:47 -0700 From: Peter Chen To: Subject: [PATCH v12 06/13] usb: chipidea: add otg_cap attribute for otg capable Date: Thu, 11 Jul 2013 14:27:14 +0800 Message-ID: <1373524041-10482-7-git-send-email-peter.chen@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1373524041-10482-1-git-send-email-peter.chen@freescale.com> References: <1373524041-10482-1-git-send-email-peter.chen@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130711_022811_975581_FEDF94CE X-CRM114-Status: GOOD ( 16.75 ) X-Spam-Score: -4.2 (----) Cc: marex@denx.de, m.grzeschik@pengutronix.de, frank.li@freescale.com, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, mkl@pengutronix.de, kernel@pengutronix.de, maxime.ripard@free-electrons.com, shawn.guo@linaro.org, festevam@gmail.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since we need otgsc to know vbus's status at some chipidea controllers even it is peripheral-only mode. Besides, some SoCs (eg, AR9331 SoC) don't have otgsc register even the DCCPARAMS_DC and DCCPARAMS_HC are both 1 at CAP_DCCPARAMS. We inroduce otg_cap attribute to indicate if the controller is otg capable, defaultly, we follow the rule that if DCCPARAMS_DC and DCCPARAMS_HC are both 1 at CAP_DCCPARAMS are otg capable, but if there is exception, the platform can override it by device tree or platform data. Signed-off-by: Peter Chen --- drivers/usb/chipidea/core.c | 35 ++++++++++++++++++++++++++++------- include/linux/usb/chipidea.h | 13 +++++++++++++ 2 files changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 93961ff..e8ceb04 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -405,6 +405,18 @@ static inline void ci_role_destroy(struct ci_hdrc *ci) ci_hdrc_host_destroy(ci); } +static void ci_get_otg_capable(struct ci_hdrc *ci) +{ + if (ci->platdata->otg_cap != OTG_CAP_ATTR_IS_NOT_EXISTED) + ci->is_otg = (ci->platdata->otg_cap == OTG_CAP_ATTR_IS_TRUE); + else + ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, + DCCPARAMS_DC | DCCPARAMS_HC) + == (DCCPARAMS_DC | DCCPARAMS_HC)); + if (ci->is_otg) + dev_dbg(ci->dev, "It is OTG capable controller\n"); +} + static int ci_hdrc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -461,6 +473,9 @@ static int ci_hdrc_probe(struct platform_device *pdev) return -ENODEV; } + /* To know if controller is OTG capable or not */ + ci_get_otg_capable(ci); + if (!ci->platdata->phy_mode) ci->platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); @@ -491,10 +506,19 @@ static int ci_hdrc_probe(struct platform_device *pdev) } if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { - ci->is_otg = true; - /* ID pin needs 1ms debouce time, we delay 2ms for safe */ - mdelay(2); - ci->role = ci_otg_role(ci); + if (ci->is_otg) { + /* ID pin needs 1ms debouce time, we delay 2ms for safe */ + mdelay(2); + ci->role = ci_otg_role(ci); + ci_hdrc_otg_init(ci); + } else { + /* + * If the controller is not OTG capable, but support + * role switch, the defalt role is gadget, and the + * user can switch it through debugfs (proc in future?) + */ + ci->role = CI_ROLE_GADGET; + } } else { ci->role = ci->roles[CI_ROLE_HOST] ? CI_ROLE_HOST @@ -514,9 +538,6 @@ static int ci_hdrc_probe(struct platform_device *pdev) if (ret) goto stop; - if (ci->is_otg) - ci_hdrc_otg_init(ci); - ret = dbg_create_files(ci); if (!ret) return 0; diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index 118bf66..0a906b4 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -7,6 +7,12 @@ #include +enum usb_otg_cap { + OTG_CAP_ATTR_IS_NOT_EXISTED = 0, + OTG_CAP_ATTR_IS_TRUE, + OTG_CAP_ATTR_IS_FALSE, +}; + struct ci_hdrc; struct ci_hdrc_platform_data { const char *name; @@ -25,6 +31,13 @@ struct ci_hdrc_platform_data { #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 void (*notify_event) (struct ci_hdrc *ci, unsigned event); struct regulator *reg_vbus; + /* + * Please only set otg_cap when the otg capability can't be + * judged by CAP_DCCPARAMS, eg, the DCCPARAMS_DC and DCCPARAMS_HC + * are both 1 at CAP_DCCPARAMS, but the controller doesn't have + * OTGSC register (eg, AR9331 SoC). + */ + enum usb_otg_cap otg_cap; }; /* Default offset of capability registers */